Lines Matching refs:VT

84   for (auto VT : {MVT::i8, MVT::i16, MVT::i32}) {  in BPFTargetLowering()
85 if (VT == MVT::i32) { in BPFTargetLowering()
89 setOperationAction(ISD::ATOMIC_LOAD_ADD, VT, Custom); in BPFTargetLowering()
92 setOperationAction(ISD::ATOMIC_LOAD_AND, VT, Custom); in BPFTargetLowering()
93 setOperationAction(ISD::ATOMIC_LOAD_OR, VT, Custom); in BPFTargetLowering()
94 setOperationAction(ISD::ATOMIC_LOAD_XOR, VT, Custom); in BPFTargetLowering()
95 setOperationAction(ISD::ATOMIC_SWAP, VT, Custom); in BPFTargetLowering()
96 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom); in BPFTargetLowering()
99 for (auto VT : { MVT::i32, MVT::i64 }) { in BPFTargetLowering()
100 if (VT == MVT::i32 && !STI.getHasAlu32()) in BPFTargetLowering()
103 setOperationAction(ISD::SDIVREM, VT, Expand); in BPFTargetLowering()
104 setOperationAction(ISD::UDIVREM, VT, Expand); in BPFTargetLowering()
105 setOperationAction(ISD::SREM, VT, Expand); in BPFTargetLowering()
106 setOperationAction(ISD::UREM, VT, Expand); in BPFTargetLowering()
107 setOperationAction(ISD::MULHU, VT, Expand); in BPFTargetLowering()
108 setOperationAction(ISD::MULHS, VT, Expand); in BPFTargetLowering()
109 setOperationAction(ISD::UMUL_LOHI, VT, Expand); in BPFTargetLowering()
110 setOperationAction(ISD::SMUL_LOHI, VT, Expand); in BPFTargetLowering()
111 setOperationAction(ISD::ROTR, VT, Expand); in BPFTargetLowering()
112 setOperationAction(ISD::ROTL, VT, Expand); in BPFTargetLowering()
113 setOperationAction(ISD::SHL_PARTS, VT, Expand); in BPFTargetLowering()
114 setOperationAction(ISD::SRL_PARTS, VT, Expand); in BPFTargetLowering()
115 setOperationAction(ISD::SRA_PARTS, VT, Expand); in BPFTargetLowering()
116 setOperationAction(ISD::CTPOP, VT, Expand); in BPFTargetLowering()
118 setOperationAction(ISD::SETCC, VT, Expand); in BPFTargetLowering()
119 setOperationAction(ISD::SELECT, VT, Expand); in BPFTargetLowering()
120 setOperationAction(ISD::SELECT_CC, VT, Custom); in BPFTargetLowering()
140 for (MVT VT : MVT::integer_valuetypes()) { in BPFTargetLowering() local
141 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in BPFTargetLowering()
142 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in BPFTargetLowering()
143 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in BPFTargetLowering()
145 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand); in BPFTargetLowering()
146 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand); in BPFTargetLowering()
147 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand); in BPFTargetLowering()
240 MVT VT) const { in getRegForInlineAsmConstraint()
254 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); in getRegForInlineAsmConstraint()
560 InVals.push_back(DAG.getConstant(0, DL, Ins[i].VT)); in LowerCallResult()
561 return DAG.getCopyFromReg(Chain, DL, 1, Ins[0].VT, InFlag).getValue(1); in LowerCallResult()
854 EVT VT) const { in getSetCCResultType()
859 EVT VT) const { in getScalarShiftAmountTy()
860 return (getHasAlu32() && VT == MVT::i32) ? MVT::i32 : MVT::i64; in getScalarShiftAmountTy()