157 void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT) {  in addTypeForNEON()  argument
158   if (VT != PromotedLdStVT) {  in addTypeForNEON()
159     setOperationAction(ISD::LOAD, VT, Promote);  in addTypeForNEON()
160     AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);  in addTypeForNEON()
162     setOperationAction(ISD::STORE, VT, Promote);  in addTypeForNEON()
163     AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);  in addTypeForNEON()
166   MVT ElemTy = VT.getVectorElementType();  in addTypeForNEON()
168     setOperationAction(ISD::SETCC, VT, Custom);  in addTypeForNEON()
169   setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);  in addTypeForNEON()
170   setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);  in addTypeForNEON()
172     setOperationAction(ISD::SINT_TO_FP, VT, Custom);  in addTypeForNEON()
173     setOperationAction(ISD::UINT_TO_FP, VT, Custom);  in addTypeForNEON()
174     setOperationAction(ISD::FP_TO_SINT, VT, Custom);  in addTypeForNEON()
175     setOperationAction(ISD::FP_TO_UINT, VT, Custom);  in addTypeForNEON()
177     setOperationAction(ISD::SINT_TO_FP, VT, Expand);  in addTypeForNEON()
178     setOperationAction(ISD::UINT_TO_FP, VT, Expand);  in addTypeForNEON()
179     setOperationAction(ISD::FP_TO_SINT, VT, Expand);  in addTypeForNEON()
180     setOperationAction(ISD::FP_TO_UINT, VT, Expand);  in addTypeForNEON()
182   setOperationAction(ISD::BUILD_VECTOR,      VT, Custom);  in addTypeForNEON()
183   setOperationAction(ISD::VECTOR_SHUFFLE,    VT, Custom);  in addTypeForNEON()
184   setOperationAction(ISD::CONCAT_VECTORS,    VT, Legal);  in addTypeForNEON()
185   setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);  in addTypeForNEON()
186   setOperationAction(ISD::SELECT,            VT, Expand);  in addTypeForNEON()
187   setOperationAction(ISD::SELECT_CC,         VT, Expand);  in addTypeForNEON()
188   setOperationAction(ISD::VSELECT,           VT, Expand);  in addTypeForNEON()
189   setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);  in addTypeForNEON()
190   if (VT.isInteger()) {  in addTypeForNEON()
191     setOperationAction(ISD::SHL, VT, Custom);  in addTypeForNEON()
192     setOperationAction(ISD::SRA, VT, Custom);  in addTypeForNEON()
193     setOperationAction(ISD::SRL, VT, Custom);  in addTypeForNEON()
197   setOperationAction(ISD::SDIV, VT, Expand);  in addTypeForNEON()
198   setOperationAction(ISD::UDIV, VT, Expand);  in addTypeForNEON()
199   setOperationAction(ISD::FDIV, VT, Expand);  in addTypeForNEON()
200   setOperationAction(ISD::SREM, VT, Expand);  in addTypeForNEON()
201   setOperationAction(ISD::UREM, VT, Expand);  in addTypeForNEON()
202   setOperationAction(ISD::FREM, VT, Expand);  in addTypeForNEON()
203   setOperationAction(ISD::SDIVREM, VT, Expand);  in addTypeForNEON()
204   setOperationAction(ISD::UDIVREM, VT, Expand);  in addTypeForNEON()
206   if (!VT.isFloatingPoint() &&  in addTypeForNEON()
207       VT != MVT::v2i64 && VT != MVT::v1i64)  in addTypeForNEON()
209       setOperationAction(Opcode, VT, Legal);  in addTypeForNEON()
210   if (!VT.isFloatingPoint())  in addTypeForNEON()
212       setOperationAction(Opcode, VT, Legal);  in addTypeForNEON()
215 void ARMTargetLowering::addDRTypeForNEON(MVT VT) {  in addDRTypeForNEON()  argument
216   addRegisterClass(VT, &ARM::DPRRegClass);  in addDRTypeForNEON()
217   addTypeForNEON(VT, MVT::f64);  in addDRTypeForNEON()
220 void ARMTargetLowering::addQRTypeForNEON(MVT VT) {  in addQRTypeForNEON()  argument
221   addRegisterClass(VT, &ARM::DPairRegClass);  in addQRTypeForNEON()
222   addTypeForNEON(VT, MVT::v2f64);  in addQRTypeForNEON()
225 void ARMTargetLowering::setAllExpand(MVT VT) {  in setAllExpand()  argument
227     setOperationAction(Opc, VT, Expand);  in setAllExpand()
232   setOperationAction(ISD::BITCAST, VT, Legal);  in setAllExpand()
233   setOperationAction(ISD::LOAD, VT, Legal);  in setAllExpand()
234   setOperationAction(ISD::STORE, VT, Legal);  in setAllExpand()
235   setOperationAction(ISD::UNDEF, VT, Legal);  in setAllExpand()
248   for (auto VT : IntTypes) {  in addMVEVectorTypes()  local
249     addRegisterClass(VT, &ARM::MQPRRegClass);  in addMVEVectorTypes()
250     setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);  in addMVEVectorTypes()
251     setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);  in addMVEVectorTypes()
252     setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);  in addMVEVectorTypes()
253     setOperationAction(ISD::BUILD_VECTOR, VT, Custom);  in addMVEVectorTypes()
254     setOperationAction(ISD::SHL, VT, Custom);  in addMVEVectorTypes()
255     setOperationAction(ISD::SRA, VT, Custom);  in addMVEVectorTypes()
256     setOperationAction(ISD::SRL, VT, Custom);  in addMVEVectorTypes()
257     setOperationAction(ISD::SMIN, VT, Legal);  in addMVEVectorTypes()
258     setOperationAction(ISD::SMAX, VT, Legal);  in addMVEVectorTypes()
259     setOperationAction(ISD::UMIN, VT, Legal);  in addMVEVectorTypes()
260     setOperationAction(ISD::UMAX, VT, Legal);  in addMVEVectorTypes()
261     setOperationAction(ISD::ABS, VT, Legal);  in addMVEVectorTypes()
262     setOperationAction(ISD::SETCC, VT, Custom);  in addMVEVectorTypes()
263     setOperationAction(ISD::MLOAD, VT, Custom);  in addMVEVectorTypes()
264     setOperationAction(ISD::MSTORE, VT, Legal);  in addMVEVectorTypes()
265     setOperationAction(ISD::CTLZ, VT, Legal);  in addMVEVectorTypes()
266     setOperationAction(ISD::CTTZ, VT, Custom);  in addMVEVectorTypes()
267     setOperationAction(ISD::BITREVERSE, VT, Legal);  in addMVEVectorTypes()
268     setOperationAction(ISD::BSWAP, VT, Legal);  in addMVEVectorTypes()
269     setOperationAction(ISD::SADDSAT, VT, Legal);  in addMVEVectorTypes()
270     setOperationAction(ISD::UADDSAT, VT, Legal);  in addMVEVectorTypes()
271     setOperationAction(ISD::SSUBSAT, VT, Legal);  in addMVEVectorTypes()
272     setOperationAction(ISD::USUBSAT, VT, Legal);  in addMVEVectorTypes()
273     setOperationAction(ISD::ABDS, VT, Legal);  in addMVEVectorTypes()
274     setOperationAction(ISD::ABDU, VT, Legal);  in addMVEVectorTypes()
277     setOperationAction(ISD::UDIV, VT, Expand);  in addMVEVectorTypes()
278     setOperationAction(ISD::SDIV, VT, Expand);  in addMVEVectorTypes()
279     setOperationAction(ISD::UREM, VT, Expand);  in addMVEVectorTypes()
280     setOperationAction(ISD::SREM, VT, Expand);  in addMVEVectorTypes()
281     setOperationAction(ISD::UDIVREM, VT, Expand);  in addMVEVectorTypes()
282     setOperationAction(ISD::SDIVREM, VT, Expand);  in addMVEVectorTypes()
283     setOperationAction(ISD::CTPOP, VT, Expand);  in addMVEVectorTypes()
284     setOperationAction(ISD::SELECT, VT, Expand);  in addMVEVectorTypes()
285     setOperationAction(ISD::SELECT_CC, VT, Expand);  in addMVEVectorTypes()
288     setOperationAction(ISD::VECREDUCE_ADD, VT, Legal);  in addMVEVectorTypes()
289     setOperationAction(ISD::VECREDUCE_SMAX, VT, Legal);  in addMVEVectorTypes()
290     setOperationAction(ISD::VECREDUCE_UMAX, VT, Legal);  in addMVEVectorTypes()
291     setOperationAction(ISD::VECREDUCE_SMIN, VT, Legal);  in addMVEVectorTypes()
292     setOperationAction(ISD::VECREDUCE_UMIN, VT, Legal);  in addMVEVectorTypes()
293     setOperationAction(ISD::VECREDUCE_MUL, VT, Custom);  in addMVEVectorTypes()
294     setOperationAction(ISD::VECREDUCE_AND, VT, Custom);  in addMVEVectorTypes()
295     setOperationAction(ISD::VECREDUCE_OR, VT, Custom);  in addMVEVectorTypes()
296     setOperationAction(ISD::VECREDUCE_XOR, VT, Custom);  in addMVEVectorTypes()
299       setOperationAction(ISD::SINT_TO_FP, VT, Expand);  in addMVEVectorTypes()
300       setOperationAction(ISD::UINT_TO_FP, VT, Expand);  in addMVEVectorTypes()
301       setOperationAction(ISD::FP_TO_SINT, VT, Expand);  in addMVEVectorTypes()
302       setOperationAction(ISD::FP_TO_UINT, VT, Expand);  in addMVEVectorTypes()
308       setIndexedLoadAction(im, VT, Legal);  in addMVEVectorTypes()
309       setIndexedStoreAction(im, VT, Legal);  in addMVEVectorTypes()
310       setIndexedMaskedLoadAction(im, VT, Legal);  in addMVEVectorTypes()
311       setIndexedMaskedStoreAction(im, VT, Legal);  in addMVEVectorTypes()
316   for (auto VT : FloatTypes) {  in addMVEVectorTypes()  local
317     addRegisterClass(VT, &ARM::MQPRRegClass);  in addMVEVectorTypes()
319       setAllExpand(VT);  in addMVEVectorTypes()
322     setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);  in addMVEVectorTypes()
323     setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);  in addMVEVectorTypes()
324     setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getVectorElementType(), Custom);  in addMVEVectorTypes()
325     setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);  in addMVEVectorTypes()
326     setOperationAction(ISD::BUILD_VECTOR, VT, Custom);  in addMVEVectorTypes()
327     setOperationAction(ISD::BUILD_VECTOR, VT.getVectorElementType(), Custom);  in addMVEVectorTypes()
328     setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Legal);  in addMVEVectorTypes()
329     setOperationAction(ISD::SETCC, VT, Custom);  in addMVEVectorTypes()
330     setOperationAction(ISD::MLOAD, VT, Custom);  in addMVEVectorTypes()
331     setOperationAction(ISD::MSTORE, VT, Legal);  in addMVEVectorTypes()
332     setOperationAction(ISD::SELECT, VT, Expand);  in addMVEVectorTypes()
333     setOperationAction(ISD::SELECT_CC, VT, Expand);  in addMVEVectorTypes()
338       setIndexedLoadAction(im, VT, Legal);  in addMVEVectorTypes()
339       setIndexedStoreAction(im, VT, Legal);  in addMVEVectorTypes()
340       setIndexedMaskedLoadAction(im, VT, Legal);  in addMVEVectorTypes()
341       setIndexedMaskedStoreAction(im, VT, Legal);  in addMVEVectorTypes()
345       setOperationAction(ISD::FMINNUM, VT, Legal);  in addMVEVectorTypes()
346       setOperationAction(ISD::FMAXNUM, VT, Legal);  in addMVEVectorTypes()
347       setOperationAction(ISD::FROUND, VT, Legal);  in addMVEVectorTypes()
348       setOperationAction(ISD::VECREDUCE_FADD, VT, Custom);  in addMVEVectorTypes()
349       setOperationAction(ISD::VECREDUCE_FMUL, VT, Custom);  in addMVEVectorTypes()
350       setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom);  in addMVEVectorTypes()
351       setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom);  in addMVEVectorTypes()
354       setOperationAction(ISD::FDIV, VT, Expand);  in addMVEVectorTypes()
355       setOperationAction(ISD::FREM, VT, Expand);  in addMVEVectorTypes()
356       setOperationAction(ISD::FSQRT, VT, Expand);  in addMVEVectorTypes()
357       setOperationAction(ISD::FSIN, VT, Expand);  in addMVEVectorTypes()
358       setOperationAction(ISD::FCOS, VT, Expand);  in addMVEVectorTypes()
359       setOperationAction(ISD::FPOW, VT, Expand);  in addMVEVectorTypes()
360       setOperationAction(ISD::FLOG, VT, Expand);  in addMVEVectorTypes()
361       setOperationAction(ISD::FLOG2, VT, Expand);  in addMVEVectorTypes()
362       setOperationAction(ISD::FLOG10, VT, Expand);  in addMVEVectorTypes()
363       setOperationAction(ISD::FEXP, VT, Expand);  in addMVEVectorTypes()
364       setOperationAction(ISD::FEXP2, VT, Expand);  in addMVEVectorTypes()
365       setOperationAction(ISD::FNEARBYINT, VT, Expand);  in addMVEVectorTypes()
384   for (auto VT : LongTypes) {  in addMVEVectorTypes()  local
385     addRegisterClass(VT, &ARM::MQPRRegClass);  in addMVEVectorTypes()
386     setAllExpand(VT);  in addMVEVectorTypes()
387     setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);  in addMVEVectorTypes()
388     setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);  in addMVEVectorTypes()
389     setOperationAction(ISD::BUILD_VECTOR, VT, Custom);  in addMVEVectorTypes()
418     for (auto VT : {MVT::v8i8, MVT::v4i8, MVT::v4i16}) {  in addMVEVectorTypes()
419       setIndexedLoadAction(im, VT, Legal);  in addMVEVectorTypes()
420       setIndexedStoreAction(im, VT, Legal);  in addMVEVectorTypes()
421       setIndexedMaskedLoadAction(im, VT, Legal);  in addMVEVectorTypes()
422       setIndexedMaskedStoreAction(im, VT, Legal);  in addMVEVectorTypes()
428   for (auto VT : pTypes) {  in addMVEVectorTypes()  local
429     addRegisterClass(VT, &ARM::VCCRRegClass);  in addMVEVectorTypes()
430     setOperationAction(ISD::BUILD_VECTOR, VT, Custom);  in addMVEVectorTypes()
431     setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);  in addMVEVectorTypes()
432     setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);  in addMVEVectorTypes()
433     setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);  in addMVEVectorTypes()
434     setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);  in addMVEVectorTypes()
435     setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);  in addMVEVectorTypes()
436     setOperationAction(ISD::SETCC, VT, Custom);  in addMVEVectorTypes()
437     setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);  in addMVEVectorTypes()
438     setOperationAction(ISD::LOAD, VT, Custom);  in addMVEVectorTypes()
439     setOperationAction(ISD::STORE, VT, Custom);  in addMVEVectorTypes()
440     setOperationAction(ISD::TRUNCATE, VT, Custom);  in addMVEVectorTypes()
441     setOperationAction(ISD::VSELECT, VT, Expand);  in addMVEVectorTypes()
442     setOperationAction(ISD::SELECT, VT, Expand);  in addMVEVectorTypes()
766   for (MVT VT : MVT::fixedlen_vector_valuetypes()) {  in ARMTargetLowering()  local
768       setTruncStoreAction(VT, InnerVT, Expand);  in ARMTargetLowering()
769       addAllExtLoads(VT, InnerVT, Expand);  in ARMTargetLowering()
772     setOperationAction(ISD::SMUL_LOHI, VT, Expand);  in ARMTargetLowering()
773     setOperationAction(ISD::UMUL_LOHI, VT, Expand);  in ARMTargetLowering()
775     setOperationAction(ISD::BSWAP, VT, Expand);  in ARMTargetLowering()
951     for (MVT VT : MVT::fixedlen_vector_valuetypes()) {  in ARMTargetLowering()  local
952       setOperationAction(ISD::MULHS, VT, Expand);  in ARMTargetLowering()
953       setOperationAction(ISD::MULHU, VT, Expand);  in ARMTargetLowering()
973       for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) {  in ARMTargetLowering()  local
974         setLoadExtAction(ISD::EXTLOAD, VT, Ty, Legal);  in ARMTargetLowering()
975         setLoadExtAction(ISD::ZEXTLOAD, VT, Ty, Legal);  in ARMTargetLowering()
976         setLoadExtAction(ISD::SEXTLOAD, VT, Ty, Legal);  in ARMTargetLowering()
1068   for (MVT VT : MVT::fp_valuetypes()) {  in ARMTargetLowering()  local
1069     setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);  in ARMTargetLowering()
1070     setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);  in ARMTargetLowering()
1079   for (MVT VT : MVT::integer_valuetypes())  in ARMTargetLowering()  local
1080     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);  in ARMTargetLowering()
1161   for (MVT VT : MVT::fixedlen_vector_valuetypes()) {  in ARMTargetLowering()  local
1162     setOperationAction(ISD::ROTL, VT, Expand);  in ARMTargetLowering()
1163     setOperationAction(ISD::ROTR, VT, Expand);  in ARMTargetLowering()
1582                                            MVT VT) const {  in findRepresentativeClass()
1585   switch (VT.SimpleTy) {  in findRepresentativeClass()
1587     return TargetLowering::findRepresentativeClass(TRI, VT);  in findRepresentativeClass()
1833                                           EVT VT) const {  in getSetCCResultType()
1834   if (!VT.isVector())  in getSetCCResultType()
1839        (VT == MVT::v4i32 || VT == MVT::v8i16 || VT == MVT::v16i8)) ||  in getSetCCResultType()
1840       (Subtarget->hasMVEFloatOps() && (VT == MVT::v4f32 || VT == MVT::v8f16)))  in getSetCCResultType()
1841     return MVT::getVectorVT(MVT::i1, VT.getVectorElementCount());  in getSetCCResultType()
1842   return VT.changeVectorElementTypeToInteger();  in getSetCCResultType()
1848 ARMTargetLowering::getRegClassFor(MVT VT, bool isDivergent) const {  in getRegClassFor()  argument
1855     if (VT == MVT::v4i64)  in getRegClassFor()
1857     if (VT == MVT::v8i64)  in getRegClassFor()
1860   return TargetLowering::getRegClassFor(VT);  in getRegClassFor()
1890     EVT VT = N->getValueType(i);  in getSchedulingPreference()  local
1891     if (VT == MVT::Glue || VT == MVT::Other)  in getSchedulingPreference()
1893     if (VT.isFloatingPoint() || VT.isVector())  in getSchedulingPreference()
2476           Outs[0].VT == MVT::i32) {  in LowerCall()
2479         assert(!Ins.empty() && Ins[0].VT == MVT::i32 &&  in LowerCall()
4886   EVT VT = Op.getValueType();  in LowerSignedALUO()  local
4888   SDValue Overflow = DAG.getNode(ARMISD::CMOV, dl, VT, TVal, FVal,  in LowerSignedALUO()
4908 static SDValue ConvertCarryFlagToBooleanCarry(SDValue Flags, EVT VT,  in ConvertCarryFlagToBooleanCarry()  argument
4914   return DAG.getNode(ARMISD::ADDE, DL, DAG.getVTList(VT, MVT::i32),  in ConvertCarryFlagToBooleanCarry()
4929   EVT VT = Op.getValueType();  in LowerUnsignedALUO()  local
4930   SDVTList VTs = DAG.getVTList(VT, MVT::i32);  in LowerUnsignedALUO()
4939     Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);  in LowerUnsignedALUO()
4944     Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);  in LowerUnsignedALUO()
4958   EVT VT = Op.getValueType();  in LowerADDSUBSAT()  local
4961   if (!VT.isSimple())  in LowerADDSUBSAT()
4965   switch (VT.getSimpleVT().SimpleTy) {  in LowerADDSUBSAT()
5007   return DAG.getNode(ISD::TRUNCATE, dl, VT, Add);  in LowerADDSUBSAT()
5027     EVT VT = Op.getValueType();  in LowerSELECT()  local
5029     return getCMOV(dl, VT, SelectTrue, SelectFalse, ARMcc, CCR,  in LowerSELECT()
5059         EVT VT = Op.getValueType();  in LowerSELECT()  local
5063         assert(True.getValueType() == VT);  in LowerSELECT()
5064         return getCMOV(dl, VT, True, False, ARMcc, CCR, Cmp, DAG);  in LowerSELECT()
5129 SDValue ARMTargetLowering::getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal,  in getCMOV()  argument
5132   if (!Subtarget->hasFP64() && VT == MVT::f64) {  in getCMOV()
5150     return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,  in getCMOV()
5196   EVT VT = Op.getValueType();  in LowerSaturatingConditional()  local
5244     return DAG.getNode(ARMISD::SSAT, dl, VT, V2Tmp,  in LowerSaturatingConditional()
5245                        DAG.getConstant(countTrailingOnes(K), dl, VT));  in LowerSaturatingConditional()
5247     return DAG.getNode(ARMISD::USAT, dl, VT, V2Tmp,  in LowerSaturatingConditional()
5248                        DAG.getConstant(countTrailingOnes(K), dl, VT));  in LowerSaturatingConditional()
5295 bool ARMTargetLowering::isUnsupportedFloatingType(EVT VT) const {  in isUnsupportedFloatingType()
5296   if (VT == MVT::f32)  in isUnsupportedFloatingType()
5298   if (VT == MVT::f64)  in isUnsupportedFloatingType()
5300   if (VT == MVT::f16)  in isUnsupportedFloatingType()
5306   EVT VT = Op.getValueType();  in LowerSELECT_CC()  local
5322   if (VT == MVT::i32 &&  in LowerSELECT_CC()
5324     SDValue ShiftV = DAG.getNode(ISD::SRA, dl, VT, SatValue,  in LowerSELECT_CC()
5325                                  DAG.getConstant(31, dl, VT));  in LowerSELECT_CC()
5327       SDValue NotShiftV = DAG.getNode(ISD::XOR, dl, VT, ShiftV,  in LowerSELECT_CC()
5328                                       DAG.getAllOnesConstant(dl, VT));  in LowerSELECT_CC()
5329       return DAG.getNode(ISD::AND, dl, VT, SatValue, NotShiftV);  in LowerSELECT_CC()
5331       return DAG.getNode(ISD::OR, dl, VT, SatValue, ShiftV);  in LowerSELECT_CC()
5385       EVT VT = TrueVal.getValueType();  in LowerSELECT_CC()  local
5386       return DAG.getNode(Opcode, dl, VT, TrueVal, FalseVal, ARMcc, Cmp);  in LowerSELECT_CC()
5430     return getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);  in LowerSELECT_CC()
5461   SDValue Result = getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);  in LowerSELECT_CC()
5466     Result = getCMOV(dl, VT, Result, TrueVal, ARMcc2, CCR, Cmp2, DAG);  in LowerSELECT_CC()
5481   EVT VT = Op.getValueType();  in canChangeToInt()  local
5482   if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())  in canChangeToInt()
5745   EVT VT = Op.getValueType();  in LowerVectorFP_TO_INT()  local
5768   if (VT != MVT::v4i16 && VT != MVT::v8i16)  in LowerVectorFP_TO_INT()
5772   return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);  in LowerVectorFP_TO_INT()
5776   EVT VT = Op.getValueType();  in LowerFP_TO_INT()  local
5777   if (VT.isVector())  in LowerFP_TO_INT()
5815   EVT VT = Op.getValueType();  in LowerVectorINT_TO_FP()  local
5819     if (VT.getVectorElementType() == MVT::f32)  in LowerVectorINT_TO_FP()
5832   if (VT == MVT::v4f32)  in LowerVectorINT_TO_FP()
5834   else if (VT == MVT::v4f16 && HasFullFP16)  in LowerVectorINT_TO_FP()
5836   else if (VT == MVT::v8f16 && HasFullFP16)  in LowerVectorINT_TO_FP()
5856   return DAG.getNode(Opc, dl, VT, Op);  in LowerVectorINT_TO_FP()
5860   EVT VT = Op.getValueType();  in LowerINT_TO_FP()  local
5861   if (VT.isVector())  in LowerINT_TO_FP()
5863   if (isUnsupportedFloatingType(VT)) {  in LowerINT_TO_FP()
5884   EVT VT = Op.getValueType();  in LowerFCOPYSIGN()  local
5895     EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;  in LowerFCOPYSIGN()
5896     if (VT == MVT::f64)  in LowerFCOPYSIGN()
5904       if (VT == MVT::f64)  in LowerFCOPYSIGN()
5908     } else if (VT == MVT::f32)  in LowerFCOPYSIGN()
5924     if (VT == MVT::f32) {  in LowerFCOPYSIGN()
5945   if (VT == MVT::f32) {  in LowerFCOPYSIGN()
5969   EVT VT = Op.getValueType();  in LowerRETURNADDR()  local
5975     return DAG.getLoad(VT, dl, DAG.getEntryNode(),  in LowerRETURNADDR()
5976                        DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),  in LowerRETURNADDR()
5982   return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);  in LowerRETURNADDR()
5992   EVT VT = Op.getValueType();  in LowerFRAMEADDR()  local
5996   SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);  in LowerFRAMEADDR()
5998     FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,  in LowerFRAMEADDR()
6005 Register ARMTargetLowering::getRegisterByName(const char* RegName, LLT VT,  in getRegisterByName()  argument
6155 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, const SDLoc &dl) {  in getZeroVector()  argument
6156   assert(VT.isVector() && "Expected a vector type");  in getZeroVector()
6159   EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;  in getZeroVector()
6161   return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);  in getZeroVector()
6169   EVT VT = Op.getValueType();  in LowerShiftRightParts()  local
6170   unsigned VTBits = VT.getSizeInBits();  in LowerShiftRightParts()
6183   SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);  in LowerShiftRightParts()
6186   SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);  in LowerShiftRightParts()
6187   SDValue LoSmallShift = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);  in LowerShiftRightParts()
6188   SDValue LoBigShift = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);  in LowerShiftRightParts()
6191   SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, LoSmallShift, LoBigShift,  in LowerShiftRightParts()
6194   SDValue HiSmallShift = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);  in LowerShiftRightParts()
6196                            ? DAG.getNode(Opc, dl, VT, ShOpHi,  in LowerShiftRightParts()
6197                                          DAG.getConstant(VTBits - 1, dl, VT))  in LowerShiftRightParts()
6198                            : DAG.getConstant(0, dl, VT);  in LowerShiftRightParts()
6201   SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, HiSmallShift, HiBigShift,  in LowerShiftRightParts()
6213   EVT VT = Op.getValueType();  in LowerShiftLeftParts()  local
6214   unsigned VTBits = VT.getSizeInBits();  in LowerShiftLeftParts()
6225   SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);  in LowerShiftLeftParts()
6226   SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);  in LowerShiftLeftParts()
6227   SDValue HiSmallShift = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);  in LowerShiftLeftParts()
6231   SDValue HiBigShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);  in LowerShiftLeftParts()
6234   SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, HiSmallShift, HiBigShift,  in LowerShiftLeftParts()
6239   SDValue LoSmallShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);  in LowerShiftLeftParts()
6240   SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, LoSmallShift,  in LowerShiftLeftParts()
6241                            DAG.getConstant(0, dl, VT), ARMcc, CCR, CmpLo);  in LowerShiftLeftParts()
6315   EVT VT = N->getValueType(0);  in LowerCTTZ()  local
6316   if (VT.isVector() && ST->hasNEON()) {  in LowerCTTZ()
6320     SDValue NX = DAG.getNode(ISD::SUB, dl, VT, getZeroVector(VT, DAG, dl), X);  in LowerCTTZ()
6321     SDValue LSB = DAG.getNode(ISD::AND, dl, VT, X, NX);  in LowerCTTZ()
6323     EVT ElemTy = VT.getVectorElementType();  in LowerCTTZ()
6327       SDValue One = DAG.getNode(ARMISD::VMOVIMM, dl, VT,  in LowerCTTZ()
6329       SDValue Bits = DAG.getNode(ISD::SUB, dl, VT, LSB, One);  in LowerCTTZ()
6330       return DAG.getNode(ISD::CTPOP, dl, VT, Bits);  in LowerCTTZ()
6338           DAG.getNode(ARMISD::VMOVIMM, dl, VT,  in LowerCTTZ()
6340       SDValue CTLZ = DAG.getNode(ISD::CTLZ, dl, VT, LSB);  in LowerCTTZ()
6341       return DAG.getNode(ISD::SUB, dl, VT, WidthMinus1, CTLZ);  in LowerCTTZ()
6350       SDValue FF = DAG.getNode(ARMISD::VMOVIMM, dl, VT,  in LowerCTTZ()
6352       Bits = DAG.getNode(ISD::ADD, dl, VT, LSB, FF);  in LowerCTTZ()
6354       SDValue One = DAG.getNode(ARMISD::VMOVIMM, dl, VT,  in LowerCTTZ()
6356       Bits = DAG.getNode(ISD::SUB, dl, VT, LSB, One);  in LowerCTTZ()
6358     return DAG.getNode(ISD::CTPOP, dl, VT, Bits);  in LowerCTTZ()
6364   SDValue rbit = DAG.getNode(ISD::BITREVERSE, dl, VT, N->getOperand(0));  in LowerCTTZ()
6365   return DAG.getNode(ISD::CTLZ, dl, VT, rbit);  in LowerCTTZ()
6370   EVT VT = N->getValueType(0);  in LowerCTPOP()  local
6374   assert((VT == MVT::v1i64 || VT == MVT::v2i64 || VT == MVT::v2i32 ||  in LowerCTPOP()
6375           VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) &&  in LowerCTPOP()
6379   EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8;  in LowerCTPOP()
6385   unsigned NumElts = VT.is64BitVector() ? 8 : 16;  in LowerCTPOP()
6386   while (EltSize != VT.getScalarSizeInBits()) {  in LowerCTPOP()
6425 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {  in isVShiftLImm()  argument
6426   assert(VT.isVector() && "vector shift count is not a vector type");  in isVShiftLImm()
6427   int64_t ElementBits = VT.getScalarSizeInBits();  in isVShiftLImm()
6439 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,  in isVShiftRImm()  argument
6441   assert(VT.isVector() && "vector shift count is not a vector type");  in isVShiftRImm()
6442   int64_t ElementBits = VT.getScalarSizeInBits();  in isVShiftRImm()
6456   EVT VT = N->getValueType(0);  in LowerShift()  local
6460   if (!VT.isVector())  in LowerShift()
6470     if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))  in LowerShift()
6471       return DAG.getNode(ARMISD::VSHLIMM, dl, VT, N->getOperand(0),  in LowerShift()
6473     return DAG.getNode(ARMISD::VSHLu, dl, VT, N->getOperand(0),  in LowerShift()
6480   if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {  in LowerShift()
6483     return DAG.getNode(VShiftOpc, dl, VT, N->getOperand(0),  in LowerShift()
6494   return DAG.getNode(VShiftOpc, dl, VT, N->getOperand(0), NegatedCount);  in LowerShift()
6499   EVT VT = N->getValueType(0);  in Expand64BitShift()  local
6503   if (VT != MVT::i64)  in Expand64BitShift()
6588   EVT VT = Op.getValueType();  in LowerVSETCC()  local
6607     CmpVT = VT;  in LowerVSETCC()
6625     Merged = DAG.getSExtOrTrunc(Merged, dl, VT);  in LowerVSETCC()
6666         Result = DAG.getNOT(dl, Result, VT);  in LowerVSETCC()
6678         Result = DAG.getNOT(dl, Result, VT);  in LowerVSETCC()
6720           Result = DAG.getNOT(dl, Result, VT);  in LowerVSETCC()
6751   Result = DAG.getSExtOrTrunc(Result, dl, VT);  in LowerVSETCC()
6754     Result = DAG.getNOT(dl, Result, VT);  in LowerVSETCC()
6794                                  const SDLoc &dl, EVT &VT, EVT VectorVT,  in isVMOVModifiedImm()  argument
6815     VT = is128Bits ? MVT::v16i8 : MVT::v8i8;  in isVMOVModifiedImm()
6820     VT = is128Bits ? MVT::v8i16 : MVT::v4i16;  in isVMOVModifiedImm()
6840     VT = is128Bits ? MVT::v4i32 : MVT::v2i32;  in isVMOVModifiedImm()
6928     VT = is128Bits ? MVT::v2i64 : MVT::v1i64;  in isVMOVModifiedImm()
6942   EVT VT = Op.getValueType();  in LowerConstantFP()  local
6943   bool IsDouble = (VT == MVT::f64);  in LowerConstantFP()
6951     if (isFPImmLegal(FPVal, VT))  in LowerConstantFP()
6956     switch (VT.getSimpleVT().SimpleTy) {  in LowerConstantFP()
6966           return DAG.getNode(ARMISD::VMOVSR, DL, VT,  in LowerConstantFP()
7015                                      VMovVT, VT, VMOVModImm);  in LowerConstantFP()
7032                              VT, VMVNModImm);  in LowerConstantFP()
7052 static bool isSingletonVEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {  in isSingletonVEXTMask()  argument
7053   unsigned NumElts = VT.getVectorNumElements();  in isSingletonVEXTMask()
7080 static bool isVEXTMask(ArrayRef<int> M, EVT VT,  in isVEXTMask()  argument
7082   unsigned NumElts = VT.getVectorNumElements();  in isVEXTMask()
7116 static bool isVTBLMask(ArrayRef<int> M, EVT VT) {  in isVTBLMask()  argument
7120   return VT == MVT::v8i8 && M.size() == 8;  in isVTBLMask()
7151 static bool isVTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {  in isVTRNMask()  argument
7152   unsigned EltSz = VT.getScalarSizeInBits();  in isVTRNMask()
7156   unsigned NumElts = VT.getVectorNumElements();  in isVTRNMask()
7183 static bool isVTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){  in isVTRN_v_undef_Mask()  argument
7184   unsigned EltSz = VT.getScalarSizeInBits();  in isVTRN_v_undef_Mask()
7188   unsigned NumElts = VT.getVectorNumElements();  in isVTRN_v_undef_Mask()
7215 static bool isVUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {  in isVUZPMask()  argument
7216   unsigned EltSz = VT.getScalarSizeInBits();  in isVUZPMask()
7220   unsigned NumElts = VT.getVectorNumElements();  in isVUZPMask()
7236   if (VT.is64BitVector() && EltSz == 32)  in isVUZPMask()
7245 static bool isVUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){  in isVUZP_v_undef_Mask()  argument
7246   unsigned EltSz = VT.getScalarSizeInBits();  in isVUZP_v_undef_Mask()
7250   unsigned NumElts = VT.getVectorNumElements();  in isVUZP_v_undef_Mask()
7272   if (VT.is64BitVector() && EltSz == 32)  in isVUZP_v_undef_Mask()
7286 static bool isVZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {  in isVZIPMask()  argument
7287   unsigned EltSz = VT.getScalarSizeInBits();  in isVZIPMask()
7291   unsigned NumElts = VT.getVectorNumElements();  in isVZIPMask()
7310   if (VT.is64BitVector() && EltSz == 32)  in isVZIPMask()
7319 static bool isVZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){  in isVZIP_v_undef_Mask()  argument
7320   unsigned EltSz = VT.getScalarSizeInBits();  in isVZIP_v_undef_Mask()
7324   unsigned NumElts = VT.getVectorNumElements();  in isVZIP_v_undef_Mask()
7343   if (VT.is64BitVector() && EltSz == 32)  in isVZIP_v_undef_Mask()
7351 static unsigned isNEONTwoResultShuffleMask(ArrayRef<int> ShuffleMask, EVT VT,  in isNEONTwoResultShuffleMask()  argument
7355   if (isVTRNMask(ShuffleMask, VT, WhichResult))  in isNEONTwoResultShuffleMask()
7357   if (isVUZPMask(ShuffleMask, VT, WhichResult))  in isNEONTwoResultShuffleMask()
7359   if (isVZIPMask(ShuffleMask, VT, WhichResult))  in isNEONTwoResultShuffleMask()
7363   if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))  in isNEONTwoResultShuffleMask()
7365   if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))  in isNEONTwoResultShuffleMask()
7367   if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))  in isNEONTwoResultShuffleMask()
7374 static bool isReverseMask(ArrayRef<int> M, EVT VT) {  in isReverseMask()  argument
7375   unsigned NumElts = VT.getVectorNumElements();  in isReverseMask()
7388 static bool isVMOVNMask(ArrayRef<int> M, EVT VT, bool Top, bool SingleSource) {  in isVMOVNMask()  argument
7389   unsigned NumElts = VT.getVectorNumElements();  in isVMOVNMask()
7391   if (NumElts != M.size() || (VT != MVT::v8i16 && VT != MVT::v16i8))  in isVMOVNMask()
7447   EVT VT = BV.getValueType();  in LowerBuildVectorOfFPTrunc()  local
7448   if (VT != MVT::v8f16)  in LowerBuildVectorOfFPTrunc()
7482   SDValue N1 = DAG.getNode(ARMISD::VCVTN, dl, VT, DAG.getUNDEF(VT), Op0,  in LowerBuildVectorOfFPTrunc()
7484   return DAG.getNode(ARMISD::VCVTN, dl, VT, N1, Op1,  in LowerBuildVectorOfFPTrunc()
7500   EVT VT = BV.getValueType();  in LowerBuildVectorOfFPExt()  local
7501   if (VT != MVT::v4f32)  in LowerBuildVectorOfFPExt()
7528   return DAG.getNode(ARMISD::VCVTL, dl, VT, Op0,  in LowerBuildVectorOfFPExt()
7555   EVT VT = Op.getValueType();  in LowerBUILD_VECTOR_i1()  local
7559   unsigned NumElts = VT.getVectorNumElements();  in LowerBUILD_VECTOR_i1()
7599   SDValue Base = DAG.getNode(ARMISD::PREDICATE_CAST, dl, VT,  in LowerBUILD_VECTOR_i1()
7605     Base = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Base, V,  in LowerBUILD_VECTOR_i1()
7618   EVT VT = Op.getValueType();  in LowerBUILD_VECTORToVIDUP()  local
7620   unsigned NumElts = VT.getVectorNumElements();  in LowerBUILD_VECTORToVIDUP()
7641   return DAG.getNode(ARMISD::VIDUP, DL, DAG.getVTList(VT, MVT::i32), Op0,  in LowerBUILD_VECTORToVIDUP()
7651   EVT VT = Op.getValueType();  in LowerBUILD_VECTOR()  local
7653   if (ST->hasMVEIntegerOps() && VT.getScalarSizeInBits() == 1)  in LowerBUILD_VECTOR()
7664       return DAG.getUNDEF(VT);  in LowerBUILD_VECTOR()
7672                             SplatBitSize, DAG, dl, VmovVT, VT, VMOVModImm);  in LowerBUILD_VECTOR()
7676         return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);  in LowerBUILD_VECTOR()
7683           VT, ST->hasMVEIntegerOps() ? MVEVMVNModImm : VMVNModImm);  in LowerBUILD_VECTOR()
7686         return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);  in LowerBUILD_VECTOR()
7690       if ((VT == MVT::v2f32 || VT == MVT::v4f32) && SplatBitSize == 32) {  in LowerBUILD_VECTOR()
7694           return DAG.getNode(ARMISD::VMOVFPIMM, dl, VT, Val);  in LowerBUILD_VECTOR()
7707         return DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, VT, VDup);  in LowerBUILD_VECTOR()
7719   unsigned NumElts = VT.getVectorNumElements();  in LowerBUILD_VECTOR()
7753     return DAG.getUNDEF(VT);  in LowerBUILD_VECTOR()
7758     return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);  in LowerBUILD_VECTOR()
7760   unsigned EltSize = VT.getScalarSizeInBits();  in LowerBUILD_VECTOR()
7780         if (VT != Value->getOperand(0).getValueType()) {  in LowerBUILD_VECTOR()
7782                              VT.getVectorNumElements();  in LowerBUILD_VECTOR()
7783           N =  DAG.getNode(ARMISD::VDUPLANE, dl, VT,  in LowerBUILD_VECTOR()
7784                  DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DAG.getUNDEF(VT),  in LowerBUILD_VECTOR()
7788           N = DAG.getNode(ARMISD::VDUPLANE, dl, VT,  in LowerBUILD_VECTOR()
7791         N = DAG.getNode(ARMISD::VDUP, dl, VT, Value);  in LowerBUILD_VECTOR()
7803           N = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Ops);  in LowerBUILD_VECTOR()
7808     if (VT.getVectorElementType().isFloatingPoint()) {  in LowerBUILD_VECTOR()
7810       MVT FVT = VT.getVectorElementType().getSimpleVT();  in LowerBUILD_VECTOR()
7820         return DAG.getNode(ISD::BITCAST, dl, VT, Val);  in LowerBUILD_VECTOR()
7825         return DAG.getNode(ARMISD::VDUP, dl, VT, Val);  in LowerBUILD_VECTOR()
7849   if (ST->hasNEON() && VT.is128BitVector() && VT != MVT::v2f64 && VT != MVT::v4f32) {  in LowerBUILD_VECTOR()
7853     EVT ExtVT = VT.getVectorElementType();  in LowerBUILD_VECTOR()
7864       return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lower, Upper);  in LowerBUILD_VECTOR()
7879     return DAG.getNode(ISD::BITCAST, dl, VT, Val);  in LowerBUILD_VECTOR()
7889     SDValue Vec = DAG.getUNDEF(VT);  in LowerBUILD_VECTOR()
7895       Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);  in LowerBUILD_VECTOR()
7909   EVT VT = Op.getValueType();  in ReconstructShuffle()  local
7910   unsigned NumElts = VT.getVectorNumElements();  in ReconstructShuffle()
7968   EVT SmallestEltTy = VT.getVectorElementType();  in ReconstructShuffle()
7975       VT.getScalarSizeInBits() / SmallestEltTy.getSizeInBits();  in ReconstructShuffle()
7976   NumElts = VT.getSizeInBits() / SmallestEltTy.getSizeInBits();  in ReconstructShuffle()
7986     uint64_t VTSize = VT.getFixedSizeInBits();  in ReconstructShuffle()
8063   for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {  in ReconstructShuffle()
8076                                VT.getScalarSizeInBits());  in ReconstructShuffle()
8102   return DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, VT, Shuffle);  in ReconstructShuffle()
8141 bool ARMTargetLowering::isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const {  in isShuffleMaskLegal()
8142   if (VT.getVectorNumElements() == 4 &&  in isShuffleMaskLegal()
8143       (VT.is128BitVector() || VT.is64BitVector())) {  in isShuffleMaskLegal()
8165   unsigned EltSize = VT.getScalarSizeInBits();  in isShuffleMaskLegal()
8167       ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||  in isShuffleMaskLegal()
8169       isVREVMask(M, VT, 64) ||  in isShuffleMaskLegal()
8170       isVREVMask(M, VT, 32) ||  in isShuffleMaskLegal()
8171       isVREVMask(M, VT, 16))  in isShuffleMaskLegal()
8174            (isVEXTMask(M, VT, ReverseVEXT, Imm) ||  in isShuffleMaskLegal()
8175             isVTBLMask(M, VT) ||  in isShuffleMaskLegal()
8176             isNEONTwoResultShuffleMask(M, VT, WhichResult, isV_UNDEF)))  in isShuffleMaskLegal()
8178   else if (Subtarget->hasNEON() && (VT == MVT::v8i16 || VT == MVT::v16i8) &&  in isShuffleMaskLegal()
8179            isReverseMask(M, VT))  in isShuffleMaskLegal()
8182            (isVMOVNMask(M, VT, true, false) ||  in isShuffleMaskLegal()
8183             isVMOVNMask(M, VT, false, false) || isVMOVNMask(M, VT, true, true)))  in isShuffleMaskLegal()
8207   EVT VT = OpLHS.getValueType();  in GeneratePerfectShuffle()  local
8213     if (VT.getVectorElementType() == MVT::i32 ||  in GeneratePerfectShuffle()
8214         VT.getVectorElementType() == MVT::f32)  in GeneratePerfectShuffle()
8215       return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);  in GeneratePerfectShuffle()
8217     if (VT.getVectorElementType() == MVT::i16 ||  in GeneratePerfectShuffle()
8218         VT.getVectorElementType() == MVT::f16)  in GeneratePerfectShuffle()
8219       return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS);  in GeneratePerfectShuffle()
8221     assert(VT.getVectorElementType() == MVT::i8);  in GeneratePerfectShuffle()
8222     return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS);  in GeneratePerfectShuffle()
8227     return DAG.getNode(ARMISD::VDUPLANE, dl, VT,  in GeneratePerfectShuffle()
8232     return DAG.getNode(ARMISD::VEXT, dl, VT,  in GeneratePerfectShuffle()
8237     return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),  in GeneratePerfectShuffle()
8241     return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),  in GeneratePerfectShuffle()
8245     return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),  in GeneratePerfectShuffle()
8275   EVT VT = OpLHS.getValueType();  in LowerReverse_VECTOR_SHUFFLEv16i8_v8i16()  local
8277   assert((VT == MVT::v8i16 || VT == MVT::v16i8) &&  in LowerReverse_VECTOR_SHUFFLEv16i8_v8i16()
8279   OpLHS = DAG.getNode(ARMISD::VREV64, DL, VT, OpLHS);  in LowerReverse_VECTOR_SHUFFLEv16i8_v8i16()
8283   unsigned ExtractNum = (VT == MVT::v16i8) ? 8 : 4;  in LowerReverse_VECTOR_SHUFFLEv16i8_v8i16()
8284   return DAG.getNode(ARMISD::VEXT, DL, VT, OpLHS, OpLHS,  in LowerReverse_VECTOR_SHUFFLEv16i8_v8i16()
8288 static EVT getVectorTyFromPredicateVector(EVT VT) {  in getVectorTyFromPredicateVector()  argument
8289   switch (VT.getSimpleVT().SimpleTy) {  in getVectorTyFromPredicateVector()
8301 static SDValue PromoteMVEPredVector(SDLoc dl, SDValue Pred, EVT VT,  in PromoteMVEPredVector()  argument
8315   EVT NewVT = getVectorTyFromPredicateVector(VT);  in PromoteMVEPredVector()
8322   if (VT != MVT::v16i1)  in PromoteMVEPredVector()
8338   EVT VT = Op.getValueType();  in LowerVECTOR_SHUFFLE_i1()  local
8347   if (isReverseMask(ShuffleMask, VT)) {  in LowerVECTOR_SHUFFLE_i1()
8352     return DAG.getNode(ARMISD::PREDICATE_CAST, dl, VT, srl);  in LowerVECTOR_SHUFFLE_i1()
8363   SDValue PredAsVector = PromoteMVEPredVector(dl, V1, VT, DAG);  in LowerVECTOR_SHUFFLE_i1()
8372   return DAG.getNode(ARMISD::VCMPZ, dl, VT, Shuffled,  in LowerVECTOR_SHUFFLE_i1()
8383   EVT VT = Op.getValueType();  in LowerVECTOR_SHUFFLEUsingMovs()  local
8384   if (VT.getScalarSizeInBits() >= 32)  in LowerVECTOR_SHUFFLEUsingMovs()
8387   assert((VT == MVT::v8i16 || VT == MVT::v8f16 || VT == MVT::v16i8) &&  in LowerVECTOR_SHUFFLEUsingMovs()
8389   int NumElts = VT.getVectorNumElements();  in LowerVECTOR_SHUFFLEUsingMovs()
8448         VT, dl, Op->getOperand(0), Op->getOperand(1), NewShuffleMask);  in LowerVECTOR_SHUFFLEUsingMovs()
8459   return DAG.getBitcast(VT, NewVec);  in LowerVECTOR_SHUFFLEUsingMovs()
8467   EVT VT = Op.getValueType();  in LowerVECTOR_SHUFFLEUsingOneOff()  local
8468   unsigned NumElts = VT.getVectorNumElements();  in LowerVECTOR_SHUFFLEUsingOneOff()
8475   auto isOneOffIdentityMask = [](ArrayRef<int> Mask, EVT VT, int BaseOffset,  in LowerVECTOR_SHUFFLEUsingOneOff()
8494   if (isOneOffIdentityMask(ShuffleMask, VT, 0, OffElement))  in LowerVECTOR_SHUFFLEUsingOneOff()
8496   else if (isOneOffIdentityMask(ShuffleMask, VT, NumElts, OffElement))  in LowerVECTOR_SHUFFLEUsingOneOff()
8502   EVT SVT = VT.getScalarType() == MVT::i8 || VT.getScalarType() == MVT::i16  in LowerVECTOR_SHUFFLEUsingOneOff()
8504                 : VT.getScalarType();  in LowerVECTOR_SHUFFLEUsingOneOff()
8509   return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, VInput, Elt,  in LowerVECTOR_SHUFFLEUsingOneOff()
8518   EVT VT = Op.getValueType();  in LowerVECTOR_SHUFFLE()  local
8520   unsigned EltSize = VT.getScalarSizeInBits();  in LowerVECTOR_SHUFFLE()
8541         return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));  in LowerVECTOR_SHUFFLE()
8555           return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));  in LowerVECTOR_SHUFFLE()
8557       return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,  in LowerVECTOR_SHUFFLE()
8563     if (ST->hasNEON() && isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {  in LowerVECTOR_SHUFFLE()
8566       return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,  in LowerVECTOR_SHUFFLE()
8570     if (isVREVMask(ShuffleMask, VT, 64))  in LowerVECTOR_SHUFFLE()
8571       return DAG.getNode(ARMISD::VREV64, dl, VT, V1);  in LowerVECTOR_SHUFFLE()
8572     if (isVREVMask(ShuffleMask, VT, 32))  in LowerVECTOR_SHUFFLE()
8573       return DAG.getNode(ARMISD::VREV32, dl, VT, V1);  in LowerVECTOR_SHUFFLE()
8574     if (isVREVMask(ShuffleMask, VT, 16))  in LowerVECTOR_SHUFFLE()
8575       return DAG.getNode(ARMISD::VREV16, dl, VT, V1);  in LowerVECTOR_SHUFFLE()
8577     if (ST->hasNEON() && V2->isUndef() && isSingletonVEXTMask(ShuffleMask, VT, Imm)) {  in LowerVECTOR_SHUFFLE()
8578       return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V1,  in LowerVECTOR_SHUFFLE()
8591               ShuffleMask, VT, WhichResult, isV_UNDEF)) {  in LowerVECTOR_SHUFFLE()
8594         return DAG.getNode(ShuffleOpc, dl, DAG.getVTList(VT, VT), V1, V2)  in LowerVECTOR_SHUFFLE()
8599       if (isVMOVNMask(ShuffleMask, VT, false, false))  in LowerVECTOR_SHUFFLE()
8600         return DAG.getNode(ARMISD::VMOVN, dl, VT, V2, V1,  in LowerVECTOR_SHUFFLE()
8602       if (isVMOVNMask(ShuffleMask, VT, true, false))  in LowerVECTOR_SHUFFLE()
8603         return DAG.getNode(ARMISD::VMOVN, dl, VT, V1, V2,  in LowerVECTOR_SHUFFLE()
8605       if (isVMOVNMask(ShuffleMask, VT, true, true))  in LowerVECTOR_SHUFFLE()
8606         return DAG.getNode(ARMISD::VMOVN, dl, VT, V1, V1,  in LowerVECTOR_SHUFFLE()
8632         return i < (int)VT.getVectorNumElements();  in LowerVECTOR_SHUFFLE()
8643         return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Res.getValue(0),  in LowerVECTOR_SHUFFLE()
8655   unsigned NumElts = VT.getVectorNumElements();  in LowerVECTOR_SHUFFLE()
8704     return DAG.getNode(ISD::BITCAST, dl, VT, Val);  in LowerVECTOR_SHUFFLE()
8707   if (ST->hasNEON() && (VT == MVT::v8i16 || VT == MVT::v16i8) && isReverseMask(ShuffleMask, VT))  in LowerVECTOR_SHUFFLE()
8710   if (ST->hasNEON() && VT == MVT::v8i8)  in LowerVECTOR_SHUFFLE()
8810   EVT VT = Vec.getValueType();  in LowerEXTRACT_VECTOR_ELT()  local
8812   if (ST->hasMVEIntegerOps() && VT.getScalarSizeInBits() == 1)  in LowerEXTRACT_VECTOR_ELT()
8828   EVT VT = Op.getValueType();  in LowerCONCAT_VECTORS_i1()  local
8831   unsigned NumElts = VT.getVectorNumElements();  in LowerCONCAT_VECTORS_i1()
8834   assert(VT.getScalarSizeInBits() == 1 &&  in LowerCONCAT_VECTORS_i1()
8845   MVT ElType = getVectorTyFromPredicateVector(VT).getScalarType().getSimpleVT();  in LowerCONCAT_VECTORS_i1()
8871   return DAG.getNode(ARMISD::VCMPZ, dl, VT, ConVec,  in LowerCONCAT_VECTORS_i1()
8877   EVT VT = Op->getValueType(0);  in LowerCONCAT_VECTORS()  local
8878   if (ST->hasMVEIntegerOps() && VT.getScalarSizeInBits() == 1)  in LowerCONCAT_VECTORS()
8905   EVT VT = Op.getValueType();  in LowerEXTRACT_SUBVECTOR()  local
8907   unsigned NumElts = VT.getVectorNumElements();  in LowerEXTRACT_SUBVECTOR()
8910   assert(VT.getScalarSizeInBits() == 1 &&  in LowerEXTRACT_SUBVECTOR()
8920   MVT ElType = getVectorTyFromPredicateVector(VT).getScalarType().getSimpleVT();  in LowerEXTRACT_SUBVECTOR()
8933   return DAG.getNode(ARMISD::VCMPZ, dl, VT, SubVec,  in LowerEXTRACT_SUBVECTOR()
8941   EVT VT = N->getValueType(0);  in LowerTruncatei1()  local
8942   assert((VT == MVT::v16i1 || VT == MVT::v8i1 || VT == MVT::v4i1) &&  in LowerTruncatei1()
8950   return DAG.getNode(ISD::SETCC, DL, VT, And, DAG.getConstant(0, DL, FromVT),  in LowerTruncatei1()
9053   EVT VT = N->getValueType(0);  in isExtendedBUILD_VECTOR()  local
9054   if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) {  in isExtendedBUILD_VECTOR()
9084       unsigned EltSize = VT.getScalarSizeInBits();  in isExtendedBUILD_VECTOR()
9223   EVT VT = N->getValueType(0);  in SkipExtensionForVMULL()  local
9224   unsigned EltSize = VT.getScalarSizeInBits() / 2;  in SkipExtensionForVMULL()
9225   unsigned NumElts = VT.getVectorNumElements();  in SkipExtensionForVMULL()
9264   EVT VT = Op.getValueType();  in LowerMUL()  local
9265   assert(VT.is128BitVector() && VT.isInteger() &&  in LowerMUL()
9297       if (VT == MVT::v2i64)  in LowerMUL()
9315     return DAG.getNode(NewOpc, DL, VT, Op0, Op1);  in LowerMUL()
9329   return DAG.getNode(N0->getOpcode(), DL, VT,  in LowerMUL()
9330                      DAG.getNode(NewOpc, DL, VT,  in LowerMUL()
9332                      DAG.getNode(NewOpc, DL, VT,  in LowerMUL()
9408   EVT VT = Op.getValueType();  in LowerSDIV()  local
9409   assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&  in LowerSDIV()
9417   if (VT == MVT::v8i8) {  in LowerSDIV()
9445   EVT VT = Op.getValueType();  in LowerUDIV()  local
9446   assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&  in LowerUDIV()
9454   if (VT == MVT::v8i8) {  in LowerUDIV()
9521   EVT VT = N->getValueType(0);  in LowerADDSUBCARRY()  local
9522   SDVTList VTs = DAG.getVTList(VT, MVT::i32);  in LowerADDSUBCARRY()
9538     Carry = ConvertCarryFlagToBooleanCarry(Result.getValue(1), VT, DAG);  in LowerADDSUBCARRY()
9552     Carry = ConvertCarryFlagToBooleanCarry(Result.getValue(1), VT, DAG);  in LowerADDSUBCARRY()
9641   EVT VT = Op.getValueType();  in LowerWindowsDIVLibCall()  local
9642   assert((VT == MVT::i32 || VT == MVT::i64) &&  in LowerWindowsDIVLibCall()
9651     Name = (VT == MVT::i32) ? "__rt_sdiv" : "__rt_sdiv64";  in LowerWindowsDIVLibCall()
9653     Name = (VT == MVT::i32) ? "__rt_udiv" : "__rt_udiv64";  in LowerWindowsDIVLibCall()
9669     .setCallee(CallingConv::ARM_AAPCS_VFP, VT.getTypeForEVT(*DAG.getContext()),  in LowerWindowsDIVLibCall()
9898   MVT VT = Op.getSimpleValueType();  in LowerMLOAD()  local
9908   SDValue ZeroVec = DAG.getNode(ARMISD::VMOVIMM, dl, VT,  in LowerMLOAD()
9911       VT, dl, N->getChain(), N->getBasePtr(), N->getOffset(), Mask, ZeroVec,  in LowerMLOAD()
9919     Combo = DAG.getNode(ISD::VSELECT, dl, VT, Mask, NewLoad, PassThru);  in LowerMLOAD()
9943   EVT VT = Op0.getValueType();  in LowerVecReduce()  local
9944   EVT EltVT = VT.getVectorElementType();  in LowerVecReduce()
9945   unsigned NumElts = VT.getVectorNumElements();  in LowerVecReduce()
9956     SDValue Rev = DAG.getNode(RevOpcode, dl, VT, Op0);  in LowerVecReduce()
9957     Op0 = DAG.getNode(BaseOpcode, dl, VT, Op0, Rev);  in LowerVecReduce()
10077   EVT VT = Op.getValueType();  in LowerFSETCC()  local
10093     SDValue Result = DAG.getNode(ISD::SETCC, dl, VT, LHS, RHS,  in LowerFSETCC()
10106   SDValue True = DAG.getConstant(1, dl, VT);  in LowerFSETCC()
10107   SDValue False =  DAG.getConstant(0, dl, VT);  in LowerFSETCC()
10111   SDValue Result = getCMOV(dl, VT, False, True, ARMcc, CCR, Cmp, DAG);  in LowerFSETCC()
10115     Result = getCMOV(dl, VT, Result, True, ARMcc, CCR, Cmp, DAG);  in LowerFSETCC()
12093     EVT VT = N->getValueType(0);  in isConditionalZeroOrAllOnes()  local
12101       OtherOp = DAG.getConstant(0, dl, VT);  in isConditionalZeroOrAllOnes()
12104       OtherOp = DAG.getConstant(1, dl, VT);  in isConditionalZeroOrAllOnes()
12106       OtherOp = DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), dl,  in isConditionalZeroOrAllOnes()
12107                                 VT);  in isConditionalZeroOrAllOnes()
12142   EVT VT = N->getValueType(0);  in combineSelectAndUse()  local
12152   SDValue FalseVal = DAG.getNode(N->getOpcode(), SDLoc(N), VT,  in combineSelectAndUse()
12158   return DAG.getNode(ISD::SELECT, SDLoc(N), VT,  in combineSelectAndUse()
12206   EVT VT = N->getValueType(0);  in AddCombineToVPADD()  local
12214   return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, Ops);  in AddCombineToVPADD()
12245   EVT VT = N->getValueType(0);  in AddCombineVUZPToVPADDL()  local
12257   unsigned NumElts = VT.getVectorNumElements();  in AddCombineVUZPToVPADDL()
12263   return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, Ops);  in AddCombineVUZPToVPADDL()
12281   EVT VT = N->getValueType(0);  in AddCombineBUILD_VECTORToVPADDL()  local
12282   if (!VT.isInteger() || VT.getVectorElementType() == MVT::i64)  in AddCombineBUILD_VECTORToVPADDL()
12332       Vec.getValueType().getVectorElementType() == VT.getVectorElementType())  in AddCombineBUILD_VECTORToVPADDL()
12351   unsigned numElem = VT.getVectorNumElements();  in AddCombineBUILD_VECTORToVPADDL()
12363   unsigned ExtOp = VT.bitsGT(tmp.getValueType()) ? ISD::ANY_EXTEND : ISD::TRUNCATE;  in AddCombineBUILD_VECTORToVPADDL()
12364   return DAG.getNode(ExtOp, dl, VT, tmp);  in AddCombineBUILD_VECTORToVPADDL()
12867   EVT VT = N->getValueType(0);  in PerformVQDMULHCombine()  local
12929       VT.getScalarSizeInBits() < ScalarType.getScalarSizeInBits() * 2)  in PerformVQDMULHCombine()
12950     return DAG.getNode(ISD::SIGN_EXTEND, DL, VT, Trunc);  in PerformVQDMULHCombine()
12967   return DAG.getNode(ISD::SIGN_EXTEND, DL, VT,  in PerformVQDMULHCombine()
13197 bool ARMTargetLowering::preferIncOfAddToSubOfNot(EVT VT) const {  in preferIncOfAddToSubOfNot()
13200       return VT.getScalarSizeInBits() <= 32;  in preferIncOfAddToSubOfNot()
13203   return VT.isScalarInteger();  in preferIncOfAddToSubOfNot()
13429   EVT VT = N->getValueType(0);  in PerformVMULCombine()  local
13433   return DAG.getNode(Opcode, DL, VT,  in PerformVMULCombine()
13434                      DAG.getNode(ISD::MUL, DL, VT, N00, N1),  in PerformVMULCombine()
13435                      DAG.getNode(ISD::MUL, DL, VT, N01, N1));  in PerformVMULCombine()
13440   EVT VT = N->getValueType(0);  in PerformMVEVMULLCombine()  local
13441   if (VT != MVT::v2i64)  in PerformMVEVMULLCombine()
13450     EVT VT = cast<VTSDNode>(Op->getOperand(1))->getVT();  in PerformMVEVMULLCombine()  local
13451     if (VT.getScalarSizeInBits() == 32)  in PerformMVEVMULLCombine()
13489       return DAG.getNode(ARMISD::VMULLs, dl, VT, New0a, New1a);  in PerformMVEVMULLCombine()
13496       return DAG.getNode(ARMISD::VMULLu, dl, VT, New0a, New1a);  in PerformMVEVMULLCombine()
13508   EVT VT = N->getValueType(0);  in PerformMULCombine()  local
13509   if (Subtarget->hasMVEIntegerOps() && VT == MVT::v2i64)  in PerformMULCombine()
13518   if (VT.is64BitVector() || VT.is128BitVector())  in PerformMULCombine()
13520   if (VT != MVT::i32)  in PerformMULCombine()
13540       Res = DAG.getNode(ISD::ADD, DL, VT,  in PerformMULCombine()
13542                         DAG.getNode(ISD::SHL, DL, VT,  in PerformMULCombine()
13548       Res = DAG.getNode(ISD::SUB, DL, VT,  in PerformMULCombine()
13549                         DAG.getNode(ISD::SHL, DL, VT,  in PerformMULCombine()
13560       Res = DAG.getNode(ISD::SUB, DL, VT,  in PerformMULCombine()
13562                         DAG.getNode(ISD::SHL, DL, VT,  in PerformMULCombine()
13568       Res = DAG.getNode(ISD::ADD, DL, VT,  in PerformMULCombine()
13570                         DAG.getNode(ISD::SHL, DL, VT,  in PerformMULCombine()
13574       Res = DAG.getNode(ISD::SUB, DL, VT,  in PerformMULCombine()
13581     Res = DAG.getNode(ISD::SHL, DL, VT,  in PerformMULCombine()
13699   EVT VT = N->getValueType(0);  in PerformANDCombine()  local
13702   if (!DAG.getTargetLoweringInfo().isTypeLegal(VT) || VT == MVT::v4i1 ||  in PerformANDCombine()
13703       VT == MVT::v8i1 || VT == MVT::v16i1)  in PerformANDCombine()
13716                                       DAG, dl, VbicVT, VT, OtherModImm);  in PerformANDCombine()
13721         return DAG.getNode(ISD::BITCAST, dl, VT, Vbic);  in PerformANDCombine()
13810   EVT VT = N->getValueType(0);  in PerformORCombineToBFI()  local
13825   if (VT != MVT::i32)  in PerformORCombineToBFI()
13851       Res = DAG.getNode(ARMISD::BFI, DL, VT, N00,  in PerformORCombineToBFI()
13878       Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),  in PerformORCombineToBFI()
13880       Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res,  in PerformORCombineToBFI()
13895       Res = DAG.getNode(ISD::SRL, DL, VT, N00,  in PerformORCombineToBFI()
13897       Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,  in PerformORCombineToBFI()
13917     Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0),  in PerformORCombineToBFI()
13964   EVT VT = N->getValueType(0);  in PerformORCombine_i1()  local
13979   SDValue NewN0 = DAG.getLogicalNOT(DL, N0, VT);  in PerformORCombine_i1()
13980   SDValue NewN1 = DAG.getLogicalNOT(DL, N1, VT);  in PerformORCombine_i1()
13981   SDValue And = DAG.getNode(ISD::AND, DL, VT, NewN0, NewN1);  in PerformORCombine_i1()
13982   return DAG.getLogicalNOT(DL, And, VT);  in PerformORCombine_i1()
13992   EVT VT = N->getValueType(0);  in PerformORCombine()  local
13995   if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))  in PerformORCombine()
13999       (VT == MVT::v4i1 || VT == MVT::v8i1 || VT == MVT::v16i1))  in PerformORCombine()
14012                             SplatBitSize, DAG, dl, VorrVT, VT, OtherModImm);  in PerformORCombine()
14017         return DAG.getNode(ISD::BITCAST, dl, VT, Vorr);  in PerformORCombine()
14034   if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() &&  in PerformORCombine()
14035       DAG.getTargetLoweringInfo().isTypeLegal(VT)) {  in PerformORCombine()
14062                 EVT CanonicalVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;  in PerformORCombine()
14067                 return DAG.getNode(ISD::BITCAST, dl, VT, Result);  in PerformORCombine()
14089   EVT VT = N->getValueType(0);  in PerformXORCombine()  local
14092   if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))  in PerformXORCombine()
14230     EVT VT = N->getValueType(0);  in PerformBFICombine()  local
14235           ISD::SRL, dl, VT, From1,  in PerformBFICombine()
14236           DAG.getConstant(NewFromMask.countTrailingZeros(), dl, VT));  in PerformBFICombine()
14237     return DAG.getNode(ARMISD::BFI, dl, VT, CombineBFI.getOperand(0), From1,  in PerformBFICombine()
14238                        DAG.getConstant(~NewToMask, dl, VT));  in PerformBFICombine()
14253     EVT VT = N->getValueType(0);  in PerformBFICombine()  local
14255     SDValue BFI1 = DAG.getNode(ARMISD::BFI, dl, VT, N0.getOperand(0),  in PerformBFICombine()
14257     return DAG.getNode(ARMISD::BFI, dl, VT, BFI1, N0.getOperand(1),  in PerformBFICombine()
14423   EVT VT = N->getValueType(0);  in PerformVMOVrhCombine()  local
14428     return DAG.getConstant(V.bitcastToAPInt().getZExtValue(), SDLoc(N), VT);  in PerformVMOVrhCombine()
14436         DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N), VT, LN0->getChain(),  in PerformVMOVrhCombine()
14446     return DAG.getNode(ARMISD::VGETLANEu, SDLoc(N), VT, N0->getOperand(0),  in PerformVMOVrhCombine()
14482   EVT VT = N->getValueType(0);  in PerformBUILD_VECTORCombine()  local
14483   if (VT.getVectorElementType() != MVT::i64 || !hasNormalLoadOperand(N))  in PerformBUILD_VECTORCombine()
14487   unsigned NumElts = VT.getVectorNumElements();  in PerformBUILD_VECTORCombine()
14496   return DAG.getNode(ISD::BITCAST, dl, VT, BV);  in PerformBUILD_VECTORCombine()
14514   EVT VT = N->getValueType(0);  in PerformARMBUILD_VECTORCombine()  local
14515   EVT EltVT = VT.getVectorElementType();  in PerformARMBUILD_VECTORCombine()
14536   unsigned NumElts = VT.getVectorNumElements();  in PerformARMBUILD_VECTORCombine()
14585   Vec = DAG.getNode(ISD::BITCAST, dl, VT, Vec);  in PerformARMBUILD_VECTORCombine()
14593   EVT VT = N->getValueType(0);  in PerformPREDICATE_CASTCombine()  local
14600     if (Op->getOperand(0).getValueType() == VT)  in PerformPREDICATE_CASTCombine()
14602     return DCI.DAG.getNode(ARMISD::PREDICATE_CAST, dl, VT, Op->getOperand(0));  in PerformPREDICATE_CASTCombine()
14609         DCI.DAG.getNode(ARMISD::PREDICATE_CAST, dl, VT, Op->getOperand(0));  in PerformPREDICATE_CASTCombine()
14610     SDValue C = DCI.DAG.getNode(ARMISD::PREDICATE_CAST, dl, VT,  in PerformPREDICATE_CASTCombine()
14612     return DCI.DAG.getNode(ISD::XOR, dl, VT, X, C);  in PerformPREDICATE_CASTCombine()
14627   EVT VT = N->getValueType(0);  in PerformVECTOR_REG_CASTCombine()  local
14633     return DAG.getNode(ISD::BITCAST, dl, VT, Op);  in PerformVECTOR_REG_CASTCombine()
14637     return DAG.getUNDEF(VT);  in PerformVECTOR_REG_CASTCombine()
14642     if (Op->getOperand(0).getValueType() == VT)  in PerformVECTOR_REG_CASTCombine()
14644     return DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, VT, Op->getOperand(0));  in PerformVECTOR_REG_CASTCombine()
14655   EVT VT = N->getValueType(0);  in PerformVCMPCombine()  local
14664     return DAG.getNode(ARMISD::VCMPZ, dl, VT, Op0, N->getOperand(2));  in PerformVCMPCombine()
14667   if (isValidMVECond(SwappedCond, VT.isFloatingPoint())) {  in PerformVCMPCombine()
14670       return DAG.getNode(ARMISD::VCMPZ, dl, VT, Op1,  in PerformVCMPCombine()
14674       return DAG.getNode(ARMISD::VCMP, dl, VT, Op1, Op0,  in PerformVCMPCombine()
14687   EVT VT = N->getValueType(0);  in PerformInsertEltCombine()  local
14689   if (VT.getVectorElementType() != MVT::i64 ||  in PerformInsertEltCombine()
14696                                  VT.getVectorNumElements());  in PerformInsertEltCombine()
14704   return DAG.getNode(ISD::BITCAST, dl, VT, InsElt);  in PerformInsertEltCombine()
14713   EVT VT = N->getValueType(0);  in PerformExtractEltToVMOVRRD()  local
14716   if (!DCI.isAfterLegalizeDAG() || VT != MVT::i32 ||  in PerformExtractEltToVMOVRRD()
14775   EVT VT = N->getValueType(0);  in PerformExtractEltCombine()  local
14781     if (VT == MVT::f16 && X.getValueType() == MVT::i32)  in PerformExtractEltCombine()
14782       return DCI.DAG.getNode(ARMISD::VMOVhr, dl, VT, X);  in PerformExtractEltCombine()
14783     if (VT == MVT::i32 && X.getValueType() == MVT::f16)  in PerformExtractEltCombine()
14784       return DCI.DAG.getNode(ARMISD::VMOVrh, dl, VT, X);  in PerformExtractEltCombine()
14785     if (VT == MVT::f32 && X.getValueType() == MVT::i32)  in PerformExtractEltCombine()
14786       return DCI.DAG.getNode(ISD::BITCAST, dl, VT, X);  in PerformExtractEltCombine()
14788     while (X.getValueType() != VT && X->getOpcode() == ISD::BITCAST)  in PerformExtractEltCombine()
14790     if (X.getValueType() == VT)  in PerformExtractEltCombine()
14825     return DCI.DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Op0.getOperand(Vec),  in PerformExtractEltCombine()
14834   EVT VT = N->getValueType(0);  in PerformSignExtendInregCombine()  local
14840     return DAG.getNode(ARMISD::VGETLANEs, SDLoc(N), VT, Op.getOperand(0),  in PerformSignExtendInregCombine()
14850   EVT VT = N->getValueType(0);  in FlattenVectorShuffle()  local
14851   if (!N->getOperand(1).isUndef() || N->getOperand(0).getValueType() != VT)  in FlattenVectorShuffle()
14872       Op0->getOperand(0).getValueType() != VT)  in FlattenVectorShuffle()
14891   EVT VT = Trunc.getValueType();  in PerformShuffleVMOVNCombine()  local
14896   if (isVMOVNTruncMask(N->getMask(), VT, 0))  in PerformShuffleVMOVNCombine()
14898         ARMISD::VMOVN, DL, VT,  in PerformShuffleVMOVNCombine()
14899         DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, Trunc.getOperand(0)),  in PerformShuffleVMOVNCombine()
14900         DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, Trunc.getOperand(1)),  in PerformShuffleVMOVNCombine()
14902   else if (isVMOVNTruncMask(N->getMask(), VT, 1))  in PerformShuffleVMOVNCombine()
14904         ARMISD::VMOVN, DL, VT,  in PerformShuffleVMOVNCombine()
14905         DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, Trunc.getOperand(1)),  in PerformShuffleVMOVNCombine()
14906         DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, Trunc.getOperand(0)),  in PerformShuffleVMOVNCombine()
14942   EVT VT = N->getValueType(0);  in PerformVECTOR_SHUFFLECombine()  local
14943   if (!TLI.isTypeLegal(VT) ||  in PerformVECTOR_SHUFFLECombine()
14948   SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT,  in PerformVECTOR_SHUFFLECombine()
14952   unsigned NumElts = VT.getVectorNumElements();  in PerformVECTOR_SHUFFLECombine()
14964   return DAG.getVectorShuffle(VT, SDLoc(N), NewConcat,  in PerformVECTOR_SHUFFLECombine()
14965                               DAG.getUNDEF(VT), NewMask);  in PerformVECTOR_SHUFFLECombine()
15346   EVT VT = N->getValueType(0);  in CombineVLDDUP()  local
15348   if (!VT.is64BitVector())  in CombineVLDDUP()
15390     Tys[n] = VT;  in CombineVLDDUP()
15427   EVT VT = N->getValueType(0);  in PerformVDUPLANECombine()  local
15431     EVT ExtractVT = VT.getVectorElementType();  in PerformVDUPLANECombine()
15437     return DCI.DAG.getNode(ARMISD::VDUP, SDLoc(N), VT, Extract);  in PerformVDUPLANECombine()
15459   if (EltSize > VT.getScalarSizeInBits())  in PerformVDUPLANECombine()
15462   return DCI.DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);  in PerformVDUPLANECombine()
15506   EVT VT = N->getValueType(0);  in PerformLOADCombine()  local
15509   if (ISD::isNormalLoad(N) && VT.isVector() &&  in PerformLOADCombine()
15510       DCI.DAG.getTargetLoweringInfo().isTypeLegal(VT))  in PerformLOADCombine()
15522   EVT VT = StVal.getValueType();  in PerformTruncatingStoreCombine()  local
15523   if (!St->isTruncatingStore() || !VT.isVector())  in PerformTruncatingStoreCombine()
15527   unsigned NumElems = VT.getVectorNumElements();  in PerformTruncatingStoreCombine()
15528   assert(StVT != VT && "Cannot truncate to the same type");  in PerformTruncatingStoreCombine()
15529   unsigned FromEltSz = VT.getScalarSizeInBits();  in PerformTruncatingStoreCombine()
15542   assert(SizeRatio * NumElems * ToEltSz == VT.getSizeInBits());  in PerformTruncatingStoreCombine()
15547   assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());  in PerformTruncatingStoreCombine()
15578                        VT.getSizeInBits() / EVT(StoreType).getSizeInBits());  in PerformTruncatingStoreCombine()
15579   assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());  in PerformTruncatingStoreCombine()
15743   EVT VT = Extract.getValueType();  in PerformExtractFpToIntStores()  local
15746   if (VT != MVT::f16 || Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)  in PerformExtractFpToIntStores()
15763   EVT NewToVT = EVT::getIntegerVT(C, VT.getSizeInBits());  in PerformExtractFpToIntStores()
15780   EVT VT = StVal.getValueType();  in PerformSTORECombine()  local
15846   if (Subtarget->hasNEON() && ISD::isNormalStore(N) && VT.isVector() &&  in PerformSTORECombine()
15847       DCI.DAG.getTargetLoweringInfo().isTypeLegal(VT))  in PerformSTORECombine()
16101     EVT VT = Ops[0].getValueType();  in PerformVECREDUCE_ADDCombine()  local
16102     if (VT == MVT::v16i8) {  in PerformVECREDUCE_ADDCombine()
16335     EVT VT = N->getOperand(1).getValueType();  in PerformIntrinsicCombine()  local
16342       if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {  in PerformIntrinsicCombine()
16346       if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {  in PerformIntrinsicCombine()
16355       if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))  in PerformIntrinsicCombine()
16361       if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))  in PerformIntrinsicCombine()
16366       if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))  in PerformIntrinsicCombine()
16378       if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))  in PerformIntrinsicCombine()
16436     EVT VT = N->getOperand(1).getValueType();  in PerformIntrinsicCombine()  local
16440     if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))  in PerformIntrinsicCombine()
16442     else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))  in PerformIntrinsicCombine()
16538   EVT VT = N->getValueType(0);  in PerformShiftCombine()  local
16539   if (N->getOpcode() == ISD::SRL && VT == MVT::i32 && ST->hasV6Ops()) {  in PerformShiftCombine()
16548         return DAG.getNode(ISD::ROTR, SDLoc(N), VT, N0, N1);  in PerformShiftCombine()
16552   if (ST->isThumb1Only() && N->getOpcode() == ISD::SHL && VT == MVT::i32 &&  in PerformShiftCombine()
16588   if (!VT.isVector() || !TLI.isTypeLegal(VT))  in PerformShiftCombine()
16590   if (ST->hasMVEIntegerOps() && VT == MVT::v2i64)  in PerformShiftCombine()
16599     if (isVShiftLImm(N->getOperand(1), VT, false, Cnt)) {  in PerformShiftCombine()
16601       return DAG.getNode(ARMISD::VSHLIMM, dl, VT, N->getOperand(0),  in PerformShiftCombine()
16608     if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {  in PerformShiftCombine()
16612       return DAG.getNode(VShiftOpc, dl, VT, N->getOperand(0),  in PerformShiftCombine()
16716     EVT VT = N->getValueType(0);  in PerformExtendCombine()  local
16720     if (VT == MVT::i32 &&  in PerformExtendCombine()
16736       return DAG.getNode(Opc, SDLoc(N), VT, Vec, Lane);  in PerformExtendCombine()
16760   EVT VT = N->getValueType(0);  in PerformMinMaxCombine()  local
16768   if (VT != MVT::v4i32 && VT != MVT::v8i16)  in PerformMinMaxCombine()
16779     if (VT == MVT::v4i32)  in PerformMinMaxCombine()
16797     if (VT == MVT::v4i32) {  in PerformMinMaxCombine()
16811     SDValue Bitcast = DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, VQMOVN);  in PerformMinMaxCombine()
16812     return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Bitcast,  in PerformMinMaxCombine()
16822     if (VT == MVT::v4i32)  in PerformMinMaxCombine()
16838     if (VT == MVT::v4i32) {  in PerformMinMaxCombine()
16852     SDValue Bitcast = DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, VQMOVN);  in PerformMinMaxCombine()
16853     return DAG.getNode(ISD::AND, DL, VT, Bitcast,  in PerformMinMaxCombine()
16854                        DAG.getConstant(ExtConst, DL, VT));  in PerformMinMaxCombine()
16935   EVT VT = X.getValueType();  in PerformCMOVToBFICombine()  local
16940     X = DAG.getNode(ISD::SRL, dl, VT, X,  in PerformCMOVToBFICombine()
16941                     DAG.getConstant(BitInX, dl, VT));  in PerformCMOVToBFICombine()
16948     APInt Mask(VT.getSizeInBits(), 0);  in PerformCMOVToBFICombine()
16950     V = DAG.getNode(ARMISD::BFI, dl, VT, V, X,  in PerformCMOVToBFICombine()
16952                     DAG.getConstant(~Mask, dl, VT));  in PerformCMOVToBFICombine()
17135   EVT VT = N->getValueType(0);  in PerformBRCONDCombine()  local
17159           ARMISD::BRCOND, dl, VT, Chain, BB, LHS->getOperand(0)->getOperand(2),  in PerformBRCONDCombine()
17175   EVT VT = N->getValueType(0);  in PerformCMOVCombine()  local
17211     Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, TrueVal, ARMcc,  in PerformCMOVCombine()
17216     Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, FalseVal, ARMcc,  in PerformCMOVCombine()
17229       return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,  in PerformCMOVCombine()
17235   if (!VT.isInteger())  in PerformCMOVCombine()
17245         SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, LHS, RHS);  in PerformCMOVCombine()
17246         Res = DAG.getNode(ISD::SRL, dl, VT, DAG.getNode(ISD::CTLZ, dl, VT, Sub),  in PerformCMOVCombine()
17258         SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, LHS, RHS);  in PerformCMOVCombine()
17259         SDVTList VTs = DAG.getVTList(VT, MVT::i32);  in PerformCMOVCombine()
17273           DAG.getNode(ARMISD::SUBS, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS);  in PerformCMOVCombine()
17276       Res = DAG.getNode(ARMISD::CMOV, dl, VT, Sub, TrueVal, ARMcc,  in PerformCMOVCombine()
17287           DAG.getNode(ARMISD::SUBS, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS);  in PerformCMOVCombine()
17290       Res = DAG.getNode(ARMISD::CMOV, dl, VT, Sub, FalseVal,  in PerformCMOVCombine()
17316     SDVTList VTs = DAG.getVTList(VT, MVT::i32);  in PerformCMOVCombine()
17319       TrueVal = DAG.getConstant(1, dl, VT);  in PerformCMOVCombine()
17324       Res = DAG.getNode(ISD::SHL, dl, VT, Res,  in PerformCMOVCombine()
17386   EVT VT = N->getValueType(0);  in PerformMVETruncCombine()  local
17391     return DAG.getUNDEF(VT);  in PerformMVETruncCombine()
17397     return DAG.getNode(ARMISD::MVETRUNC, DL, VT, N->getOperand(0).getOperand(0),  in PerformMVETruncCombine()
17415       if (isVMOVNTruncMask(Mask, VT, 0))  in PerformMVETruncCombine()
17417             ARMISD::VMOVN, DL, VT,  in PerformMVETruncCombine()
17418             DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, S0->getOperand(0)),  in PerformMVETruncCombine()
17419             DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, S0->getOperand(1)),  in PerformMVETruncCombine()
17421       if (isVMOVNTruncMask(Mask, VT, 1))  in PerformMVETruncCombine()
17423             ARMISD::VMOVN, DL, VT,  in PerformMVETruncCombine()
17424             DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, S0->getOperand(1)),  in PerformMVETruncCombine()
17425             DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, S0->getOperand(0)),  in PerformMVETruncCombine()
17447     return DAG.getBuildVector(VT, DL, Extracts);  in PerformMVETruncCombine()
17462   EVT StoreVT = VT.getHalfNumVectorElementsVT(*DAG.getContext());  in PerformMVETruncCombine()
17481   return DAG.getLoad(VT, DL, Chain, StackPtr, MPI, Align(4));  in PerformMVETruncCombine()
17555   EVT VT = N->getValueType(0);  in PerformMVEExtCombine()  local
17558   assert((VT == MVT::v4i32 || VT == MVT::v8i16) && "Unexpected MVEEXT type");  in PerformMVEExtCombine()
17563     SDValue VVT = DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, V);  in PerformMVEExtCombine()
17565                ? DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, VVT,  in PerformMVEExtCombine()
17579     assert(Mask.size() == 2 * VT.getVectorNumElements());  in PerformMVEExtCombine()
17581     unsigned Rev = VT == MVT::v4i32 ? ARMISD::VREV32 : ARMISD::VREV16;  in PerformMVEExtCombine()
17586       for (int Idx = 0, E = VT.getVectorNumElements(); Idx < E; ++Idx)  in PerformMVEExtCombine()
17602     if (CheckInregMask(VT.getVectorNumElements(), Mask.size()))  in PerformMVEExtCombine()
17604     else if (CheckInregMask(VT.getVectorNumElements(), Mask.size() + 1))  in PerformMVEExtCombine()
17606     else if (CheckInregMask(VT.getVectorNumElements(), 0))  in PerformMVEExtCombine()
17608     else if (CheckInregMask(VT.getVectorNumElements(), 1))  in PerformMVEExtCombine()
17649         VT, Chain, Ptr, MPI, LoadVT, Align(4));  in PerformMVEExtCombine()
17852                                                           EVT VT) const {  in isDesirableToTransformToIntegerOp()
17853   return (VT == MVT::f32) && (Opc == ISD::LOAD || Opc == ISD::STORE);  in isDesirableToTransformToIntegerOp()
17856 bool ARMTargetLowering::allowsMisalignedMemoryAccesses(EVT VT, unsigned,  in allowsMisalignedMemoryAccesses()  argument
17861   if (!VT.isSimple())  in allowsMisalignedMemoryAccesses()
17866   auto Ty = VT.getSimpleVT().SimpleTy;  in allowsMisalignedMemoryAccesses()
17901       Alignment >= VT.getScalarSizeInBits() / 8) {  in allowsMisalignedMemoryAccesses()
17994 bool ARMTargetLowering::isFNegFree(EVT VT) const {  in isFNegFree()
17995   if (!VT.isSimple())  in isFNegFree()
18003   switch (VT.getSimpleVT().SimpleTy) {  in isFNegFree()
18160   EVT VT = ExtVal.getValueType();  in isVectorLoadExtDesirable()  local
18162   if (!isTypeLegal(VT))  in isVectorLoadExtDesirable()
18228                                                    EVT VT) const {  in isFMAFasterThanFMulAndFAdd()
18229   if (!VT.isSimple())  in isFMAFasterThanFMulAndFAdd()
18232   switch (VT.getSimpleVT().SimpleTy) {  in isFMAFasterThanFMulAndFAdd()
18249 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {  in isLegalT1AddressImmediate()  argument
18254   switch (VT.getSimpleVT().SimpleTy) {  in isLegalT1AddressImmediate()
18275 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,  in isLegalT2AddressImmediate()  argument
18277   if (!VT.isInteger() && !VT.isFloatingPoint())  in isLegalT2AddressImmediate()
18279   if (VT.isVector() && Subtarget->hasNEON())  in isLegalT2AddressImmediate()
18281   if (VT.isVector() && VT.isFloatingPoint() && Subtarget->hasMVEIntegerOps() &&  in isLegalT2AddressImmediate()
18291   unsigned NumBytes = std::max((unsigned)VT.getSizeInBits() / 8, 1U);  in isLegalT2AddressImmediate()
18294   if (VT.isVector() && Subtarget->hasMVEIntegerOps()) {  in isLegalT2AddressImmediate()
18295     switch (VT.getSimpleVT().getVectorElementType().SimpleTy) {  in isLegalT2AddressImmediate()
18310   if (VT.isFloatingPoint() && NumBytes == 2 && Subtarget->hasFPRegs16())  in isLegalT2AddressImmediate()
18313   if ((VT.isFloatingPoint() && Subtarget->hasVFP2Base()) || NumBytes == 8)  in isLegalT2AddressImmediate()
18329 static bool isLegalAddressImmediate(int64_t V, EVT VT,  in isLegalAddressImmediate()  argument
18334   if (!VT.isSimple())  in isLegalAddressImmediate()
18338     return isLegalT1AddressImmediate(V, VT);  in isLegalAddressImmediate()
18340     return isLegalT2AddressImmediate(V, VT, Subtarget);  in isLegalAddressImmediate()
18345   switch (VT.getSimpleVT().SimpleTy) {  in isLegalAddressImmediate()
18364                                                       EVT VT) const {  in isLegalT2ScaledAddressingMode()
18369   switch (VT.getSimpleVT().SimpleTy) {  in isLegalT2ScaledAddressingMode()
18402                                                       EVT VT) const {  in isLegalT1ScaledAddressingMode()
18421   EVT VT = getValueType(DL, Ty, true);  in isLegalAddressingMode()  local
18422   if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))  in isLegalAddressingMode()
18437     if (!VT.isSimple())  in isLegalAddressingMode()
18441       return isLegalT1ScaledAddressingMode(AM, VT);  in isLegalAddressingMode()
18444       return isLegalT2ScaledAddressingMode(AM, VT);  in isLegalAddressingMode()
18447     switch (VT.getSimpleVT().SimpleTy) {  in isLegalAddressingMode()
18511 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,  in getARMIndexedAddressParts()  argument
18518   if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {  in getARMIndexedAddressParts()
18533   } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {  in getARMIndexedAddressParts()
18570 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,  in getT2IndexedAddressParts()  argument
18595 static bool getMVEIndexedAddressParts(SDNode *Ptr, EVT VT, Align Alignment,  in getMVEIndexedAddressParts()  argument
18629   if (VT == MVT::v4i16) {  in getMVEIndexedAddressParts()
18632   } else if (VT == MVT::v4i8 || VT == MVT::v8i8) {  in getMVEIndexedAddressParts()
18636              (CanChangeType || VT == MVT::v4i32 || VT == MVT::v4f32) &&  in getMVEIndexedAddressParts()
18640            (CanChangeType || VT == MVT::v8i16 || VT == MVT::v8f16) &&  in getMVEIndexedAddressParts()
18643   else if ((CanChangeType || VT == MVT::v16i8) && IsInRange(RHSC, 0x80, 1))  in getMVEIndexedAddressParts()
18659   EVT VT;  in getPreIndexedAddressParts()  local
18666     VT = LD->getMemoryVT();  in getPreIndexedAddressParts()
18671     VT = ST->getMemoryVT();  in getPreIndexedAddressParts()
18675     VT = LD->getMemoryVT();  in getPreIndexedAddressParts()
18681     VT = ST->getMemoryVT();  in getPreIndexedAddressParts()
18689   if (VT.isVector())  in getPreIndexedAddressParts()
18692                   Ptr.getNode(), VT, Alignment, isSEXTLoad, IsMasked,  in getPreIndexedAddressParts()
18696       isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,  in getPreIndexedAddressParts()
18699       isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,  in getPreIndexedAddressParts()
18717   EVT VT;  in getPostIndexedAddressParts()  local
18723     VT = LD->getMemoryVT();  in getPostIndexedAddressParts()
18729     VT = ST->getMemoryVT();  in getPostIndexedAddressParts()
18734     VT = LD->getMemoryVT();  in getPostIndexedAddressParts()
18741     VT = ST->getMemoryVT();  in getPostIndexedAddressParts()
18769   if (VT.isVector())  in getPostIndexedAddressParts()
18771               getMVEIndexedAddressParts(Op, VT, Alignment, isSEXTLoad, IsMasked,  in getPostIndexedAddressParts()
18776       isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,  in getPostIndexedAddressParts()
18779       isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,  in getPostIndexedAddressParts()
18843       EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();  in computeKnownBitsForTargetNode()  local
18844       unsigned MemBits = VT.getScalarSizeInBits();  in computeKnownBitsForTargetNode()
18876     EVT VT = Op.getValueType();  in computeKnownBitsForTargetNode()  local
18877     const unsigned DstSz = VT.getScalarSizeInBits();  in computeKnownBitsForTargetNode()
18933   EVT VT = Op.getValueType();  in targetShrinkDemandedConstant()  local
18936   if (VT.isVector())  in targetShrinkDemandedConstant()
18939   assert(VT == MVT::i32 && "Unexpected integer type");  in targetShrinkDemandedConstant()
18966   auto UseMask = [Mask, Op, VT, &TLO](unsigned NewMask) -> bool {  in targetShrinkDemandedConstant()
18970     SDValue NewC = TLO.DAG.getConstant(NewMask, DL, VT);  in targetShrinkDemandedConstant()
18971     SDValue NewOp = TLO.DAG.getNode(ISD::AND, DL, VT, Op.getOperand(0), NewC);  in targetShrinkDemandedConstant()
19154     const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {  in getRegForInlineAsmConstraint()
19172       if (VT == MVT::Other)  in getRegForInlineAsmConstraint()
19174       if (VT == MVT::f32)  in getRegForInlineAsmConstraint()
19176       if (VT.getSizeInBits() == 64)  in getRegForInlineAsmConstraint()
19178       if (VT.getSizeInBits() == 128)  in getRegForInlineAsmConstraint()
19182       if (VT == MVT::Other)  in getRegForInlineAsmConstraint()
19184       if (VT == MVT::f32)  in getRegForInlineAsmConstraint()
19186       if (VT.getSizeInBits() == 64)  in getRegForInlineAsmConstraint()
19188       if (VT.getSizeInBits() == 128)  in getRegForInlineAsmConstraint()
19192       if (VT == MVT::Other)  in getRegForInlineAsmConstraint()
19194       if (VT == MVT::f32 || VT == MVT::i32)  in getRegForInlineAsmConstraint()
19196       if (VT.getSizeInBits() == 64)  in getRegForInlineAsmConstraint()
19198       if (VT.getSizeInBits() == 128)  in getRegForInlineAsmConstraint()
19224   return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);  in getRegForInlineAsmConstraint()
19444   EVT VT = Op->getValueType(0);  in LowerDivRem()  local
19445   Type *Ty = VT.getTypeForEVT(*DAG.getContext());  in LowerDivRem()
19460     SDValue Div = DAG.getNode(DivOpcode, dl, VT, Dividend, Divisor);  in LowerDivRem()
19461     SDValue Mul = DAG.getNode(ISD::MUL, dl, VT, Div, Divisor);  in LowerDivRem()
19462     SDValue Rem = DAG.getNode(ISD::SUB, dl, VT, Dividend, Mul);  in LowerDivRem()
19465     return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(VT, VT), Values);  in LowerDivRem()
19469                                        VT.getSimpleVT().SimpleTy);  in LowerDivRem()
19722 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,  in isFPImmLegal()  argument
19726   if (VT == MVT::f16 && Subtarget->hasFullFP16())  in isFPImmLegal()
19728   if (VT == MVT::f32 && Subtarget->hasFullFP16() &&  in isFPImmLegal()
19731   if (VT == MVT::f32)  in isFPImmLegal()
19733   if (VT == MVT::f64 && Subtarget->hasFP64())  in isFPImmLegal()
20677   } else if (auto *VT = dyn_cast<VectorType>(Ty)) {  in isHomogeneousAggregate()  local
20684       return VT->getPrimitiveSizeInBits().getFixedSize() == 64;  in isHomogeneousAggregate()
20686       return VT->getPrimitiveSizeInBits().getFixedSize() == 128;  in isHomogeneousAggregate()
20688       switch (VT->getPrimitiveSizeInBits().getFixedSize()) {  in isHomogeneousAggregate()