Lines Matching refs:VT
216 RTLIB::Libcall RTLIB::getFPLibCall(EVT VT, in getFPLibCall() argument
223 VT == MVT::f32 ? Call_F32 : in getFPLibCall()
224 VT == MVT::f64 ? Call_F64 : in getFPLibCall()
225 VT == MVT::f80 ? Call_F80 : in getFPLibCall()
226 VT == MVT::f128 ? Call_F128 : in getFPLibCall()
227 VT == MVT::ppcf128 ? Call_PPCF128 : in getFPLibCall()
495 MVT VT) { in getOUTLINE_ATOMIC() argument
497 switch (VT.SimpleTy) { in getOUTLINE_ATOMIC()
571 RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) { in getSYNC() argument
574 switch (VT.SimpleTy) { \ in getSYNC()
739 for (MVT VT : MVT::fp_valuetypes()) { in initActions() local
740 MVT IntVT = MVT::getIntegerVT(VT.getFixedSizeInBits()); in initActions()
742 setOperationAction(ISD::ATOMIC_SWAP, VT, Promote); in initActions()
743 AddPromotedToType(ISD::ATOMIC_SWAP, VT, IntVT); in initActions()
748 for (MVT VT : MVT::all_valuetypes()) { in initActions() local
752 setIndexedLoadAction(IM, VT, Expand); in initActions()
753 setIndexedStoreAction(IM, VT, Expand); in initActions()
754 setIndexedMaskedLoadAction(IM, VT, Expand); in initActions()
755 setIndexedMaskedStoreAction(IM, VT, Expand); in initActions()
759 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Expand); in initActions()
762 setOperationAction(ISD::FGETSIGN, VT, Expand); in initActions()
763 setOperationAction(ISD::CONCAT_VECTORS, VT, Expand); in initActions()
764 setOperationAction(ISD::FMINNUM, VT, Expand); in initActions()
765 setOperationAction(ISD::FMAXNUM, VT, Expand); in initActions()
766 setOperationAction(ISD::FMINNUM_IEEE, VT, Expand); in initActions()
767 setOperationAction(ISD::FMAXNUM_IEEE, VT, Expand); in initActions()
768 setOperationAction(ISD::FMINIMUM, VT, Expand); in initActions()
769 setOperationAction(ISD::FMAXIMUM, VT, Expand); in initActions()
770 setOperationAction(ISD::FMAD, VT, Expand); in initActions()
771 setOperationAction(ISD::SMIN, VT, Expand); in initActions()
772 setOperationAction(ISD::SMAX, VT, Expand); in initActions()
773 setOperationAction(ISD::UMIN, VT, Expand); in initActions()
774 setOperationAction(ISD::UMAX, VT, Expand); in initActions()
775 setOperationAction(ISD::ABS, VT, Expand); in initActions()
776 setOperationAction(ISD::FSHL, VT, Expand); in initActions()
777 setOperationAction(ISD::FSHR, VT, Expand); in initActions()
778 setOperationAction(ISD::SADDSAT, VT, Expand); in initActions()
779 setOperationAction(ISD::UADDSAT, VT, Expand); in initActions()
780 setOperationAction(ISD::SSUBSAT, VT, Expand); in initActions()
781 setOperationAction(ISD::USUBSAT, VT, Expand); in initActions()
782 setOperationAction(ISD::SSHLSAT, VT, Expand); in initActions()
783 setOperationAction(ISD::USHLSAT, VT, Expand); in initActions()
784 setOperationAction(ISD::SMULFIX, VT, Expand); in initActions()
785 setOperationAction(ISD::SMULFIXSAT, VT, Expand); in initActions()
786 setOperationAction(ISD::UMULFIX, VT, Expand); in initActions()
787 setOperationAction(ISD::UMULFIXSAT, VT, Expand); in initActions()
788 setOperationAction(ISD::SDIVFIX, VT, Expand); in initActions()
789 setOperationAction(ISD::SDIVFIXSAT, VT, Expand); in initActions()
790 setOperationAction(ISD::UDIVFIX, VT, Expand); in initActions()
791 setOperationAction(ISD::UDIVFIXSAT, VT, Expand); in initActions()
792 setOperationAction(ISD::FP_TO_SINT_SAT, VT, Expand); in initActions()
793 setOperationAction(ISD::FP_TO_UINT_SAT, VT, Expand); in initActions()
796 setOperationAction(ISD::SADDO, VT, Expand); in initActions()
797 setOperationAction(ISD::SSUBO, VT, Expand); in initActions()
798 setOperationAction(ISD::UADDO, VT, Expand); in initActions()
799 setOperationAction(ISD::USUBO, VT, Expand); in initActions()
800 setOperationAction(ISD::SMULO, VT, Expand); in initActions()
801 setOperationAction(ISD::UMULO, VT, Expand); in initActions()
804 setOperationAction(ISD::ADDCARRY, VT, Expand); in initActions()
805 setOperationAction(ISD::SUBCARRY, VT, Expand); in initActions()
806 setOperationAction(ISD::SETCCCARRY, VT, Expand); in initActions()
807 setOperationAction(ISD::SADDO_CARRY, VT, Expand); in initActions()
808 setOperationAction(ISD::SSUBO_CARRY, VT, Expand); in initActions()
811 setOperationAction(ISD::ADDC, VT, Expand); in initActions()
812 setOperationAction(ISD::ADDE, VT, Expand); in initActions()
813 setOperationAction(ISD::SUBC, VT, Expand); in initActions()
814 setOperationAction(ISD::SUBE, VT, Expand); in initActions()
817 setOperationAction(ISD::ABDS, VT, Expand); in initActions()
818 setOperationAction(ISD::ABDU, VT, Expand); in initActions()
821 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand); in initActions()
822 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand); in initActions()
824 setOperationAction(ISD::BITREVERSE, VT, Expand); in initActions()
825 setOperationAction(ISD::PARITY, VT, Expand); in initActions()
828 setOperationAction(ISD::FROUND, VT, Expand); in initActions()
829 setOperationAction(ISD::FROUNDEVEN, VT, Expand); in initActions()
830 setOperationAction(ISD::FPOWI, VT, Expand); in initActions()
833 if (VT.isVector()) { in initActions()
834 setOperationAction(ISD::FCOPYSIGN, VT, Expand); in initActions()
835 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand); in initActions()
836 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, VT, Expand); in initActions()
837 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Expand); in initActions()
838 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Expand); in initActions()
839 setOperationAction(ISD::SPLAT_VECTOR, VT, Expand); in initActions()
844 setOperationAction(ISD::STRICT_##DAGN, VT, Expand); in initActions()
848 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, VT, Expand); in initActions()
851 setOperationAction(ISD::VECREDUCE_FADD, VT, Expand); in initActions()
852 setOperationAction(ISD::VECREDUCE_FMUL, VT, Expand); in initActions()
853 setOperationAction(ISD::VECREDUCE_ADD, VT, Expand); in initActions()
854 setOperationAction(ISD::VECREDUCE_MUL, VT, Expand); in initActions()
855 setOperationAction(ISD::VECREDUCE_AND, VT, Expand); in initActions()
856 setOperationAction(ISD::VECREDUCE_OR, VT, Expand); in initActions()
857 setOperationAction(ISD::VECREDUCE_XOR, VT, Expand); in initActions()
858 setOperationAction(ISD::VECREDUCE_SMAX, VT, Expand); in initActions()
859 setOperationAction(ISD::VECREDUCE_SMIN, VT, Expand); in initActions()
860 setOperationAction(ISD::VECREDUCE_UMAX, VT, Expand); in initActions()
861 setOperationAction(ISD::VECREDUCE_UMIN, VT, Expand); in initActions()
862 setOperationAction(ISD::VECREDUCE_FMAX, VT, Expand); in initActions()
863 setOperationAction(ISD::VECREDUCE_FMIN, VT, Expand); in initActions()
864 setOperationAction(ISD::VECREDUCE_SEQ_FADD, VT, Expand); in initActions()
865 setOperationAction(ISD::VECREDUCE_SEQ_FMUL, VT, Expand); in initActions()
868 setOperationAction(ISD::VECTOR_SPLICE, VT, Expand); in initActions()
887 for (MVT VT : {MVT::f32, MVT::f64, MVT::f128}) { in initActions()
888 setOperationAction(ISD::FCBRT, VT, Expand); in initActions()
889 setOperationAction(ISD::FLOG , VT, Expand); in initActions()
890 setOperationAction(ISD::FLOG2, VT, Expand); in initActions()
891 setOperationAction(ISD::FLOG10, VT, Expand); in initActions()
892 setOperationAction(ISD::FEXP , VT, Expand); in initActions()
893 setOperationAction(ISD::FEXP2, VT, Expand); in initActions()
894 setOperationAction(ISD::FFLOOR, VT, Expand); in initActions()
895 setOperationAction(ISD::FNEARBYINT, VT, Expand); in initActions()
896 setOperationAction(ISD::FCEIL, VT, Expand); in initActions()
897 setOperationAction(ISD::FRINT, VT, Expand); in initActions()
898 setOperationAction(ISD::FTRUNC, VT, Expand); in initActions()
899 setOperationAction(ISD::FROUND, VT, Expand); in initActions()
900 setOperationAction(ISD::FROUNDEVEN, VT, Expand); in initActions()
901 setOperationAction(ISD::LROUND, VT, Expand); in initActions()
902 setOperationAction(ISD::LLROUND, VT, Expand); in initActions()
903 setOperationAction(ISD::LRINT, VT, Expand); in initActions()
904 setOperationAction(ISD::LLRINT, VT, Expand); in initActions()
931 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const { in canOpTrap()
932 assert(isTypeLegal(VT)); in canOpTrap()
956 TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const { in getTypeConversion()
958 if (VT.isSimple()) { in getTypeConversion()
959 MVT SVT = VT.getSimpleVT(); in getTypeConversion()
978 if (!VT.isVector()) { in getTypeConversion()
979 assert(VT.isInteger() && "Float types must be simple"); in getTypeConversion()
980 unsigned BitSize = VT.getSizeInBits(); in getTypeConversion()
983 EVT NVT = VT.getRoundIntegerType(Context); in getTypeConversion()
984 assert(NVT != VT && "Unable to round integer VT"); in getTypeConversion()
994 EVT::getIntegerVT(Context, VT.getSizeInBits() / 2)); in getTypeConversion()
998 ElementCount NumElts = VT.getVectorElementCount(); in getTypeConversion()
999 EVT EltVT = VT.getVectorElementType(); in getTypeConversion()
1011 if (!VT.isPow2VectorType()) { in getTypeConversion()
1023 if (VT.getVectorElementCount().isScalable()) in getTypeConversion()
1026 VT.getHalfNumVectorElementsVT(Context)); in getTypeConversion()
1081 if (!VT.isPow2VectorType()) { in getTypeConversion()
1082 EVT NVT = VT.getPow2VectorType(Context); in getTypeConversion()
1086 if (VT.getVectorElementCount() == ElementCount::getScalable(1)) in getTypeConversion()
1091 VT.getVectorElementCount().divideCoefficientBy(2)); in getTypeConversion()
1095 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, in getVectorTypeBreakdownMVT() argument
1100 ElementCount EC = VT.getVectorElementCount(); in getVectorTypeBreakdownMVT()
1101 MVT EltTy = VT.getVectorElementType(); in getVectorTypeBreakdownMVT()
1107 if (VT.isScalableVector() && !isPowerOf2_32(EC.getKnownMinValue())) in getVectorTypeBreakdownMVT()
1258 MVT VT) const { in findRepresentativeClass()
1259 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; in findRepresentativeClass()
1391 MVT VT = (MVT::SimpleValueType) i; in computeRegisterProperties() local
1392 if (isTypeLegal(VT)) in computeRegisterProperties()
1395 MVT EltVT = VT.getVectorElementType(); in computeRegisterProperties()
1396 ElementCount EC = VT.getVectorElementCount(); in computeRegisterProperties()
1398 bool IsScalable = VT.isScalableVector(); in computeRegisterProperties()
1399 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT); in computeRegisterProperties()
1417 ValueTypeActions.setTypeAction(VT, TypePromoteInteger); in computeRegisterProperties()
1440 ValueTypeActions.setTypeAction(VT, TypeWidenVector); in computeRegisterProperties()
1449 MVT NVT = VT.getPow2VectorType(); in computeRegisterProperties()
1452 ValueTypeActions.setTypeAction(VT, TypeWidenVector); in computeRegisterProperties()
1465 unsigned NumRegisters = getVectorTypeBreakdownMVT(VT, IntermediateVT, in computeRegisterProperties()
1472 MVT NVT = VT.getPow2VectorType(); in computeRegisterProperties()
1473 if (NVT == VT) { in computeRegisterProperties()
1477 ValueTypeActions.setTypeAction(VT, TypeScalarizeVector); in computeRegisterProperties()
1479 ValueTypeActions.setTypeAction(VT, TypeSplitVector); in computeRegisterProperties()
1481 ValueTypeActions.setTypeAction(VT, TypeSplitVector); in computeRegisterProperties()
1483 ValueTypeActions.setTypeAction(VT, EC.isScalable() in computeRegisterProperties()
1488 ValueTypeActions.setTypeAction(VT, TypeWidenVector); in computeRegisterProperties()
1512 EVT VT) const { in getSetCCResultType()
1513 assert(!VT.isVector() && "No default SetCC type for vectors!"); in getSetCCResultType()
1530 EVT VT, EVT &IntermediateVT, in getVectorTypeBreakdown() argument
1533 ElementCount EltCnt = VT.getVectorElementCount(); in getVectorTypeBreakdown()
1540 LegalizeTypeAction TA = getTypeAction(Context, VT); in getVectorTypeBreakdown()
1543 EVT RegisterEVT = getTypeToTransformTo(Context, VT); in getVectorTypeBreakdown()
1553 EVT EltTy = VT.getVectorElementType(); in getVectorTypeBreakdown()
1559 if (VT.isScalableVector() && !isPowerOf2_32(EltCnt.getKnownMinValue())) { in getVectorTypeBreakdown()
1561 EVT PartVT = VT; in getVectorTypeBreakdown()
1568 NumIntermediates = VT.getVectorElementCount().getKnownMinValue() / in getVectorTypeBreakdown()
1576 VT.getVectorElementCount() && in getVectorTypeBreakdown()
1657 EVT VT = ValueVTs[j]; in GetReturnInfo() local
1669 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { in GetReturnInfo()
1671 if (VT.bitsLT(MinVT)) in GetReturnInfo()
1672 VT = MinVT; in GetReturnInfo()
1676 TLI.getNumRegistersForCallingConv(ReturnType->getContext(), CC, VT); in GetReturnInfo()
1678 TLI.getRegisterTypeForCallingConv(ReturnType->getContext(), CC, VT); in GetReturnInfo()
1692 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isfixed=*/true, 0, 0)); in GetReturnInfo()
1705 LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace, in allowsMemoryAccessForAlignment() argument
1712 Type *Ty = VT.getTypeForEVT(Context); in allowsMemoryAccessForAlignment()
1713 if (VT.isZeroSized() || Alignment >= DL.getABITypeAlign(Ty)) { in allowsMemoryAccessForAlignment()
1721 return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Flags, Fast); in allowsMemoryAccessForAlignment()
1725 LLVMContext &Context, const DataLayout &DL, EVT VT, in allowsMemoryAccessForAlignment() argument
1727 return allowsMemoryAccessForAlignment(Context, DL, VT, MMO.getAddrSpace(), in allowsMemoryAccessForAlignment()
1732 const DataLayout &DL, EVT VT, in allowsMemoryAccess() argument
1736 return allowsMemoryAccessForAlignment(Context, DL, VT, AddrSpace, Alignment, in allowsMemoryAccess()
1741 const DataLayout &DL, EVT VT, in allowsMemoryAccess() argument
1744 return allowsMemoryAccess(Context, DL, VT, MMO.getAddrSpace(), MMO.getAlign(), in allowsMemoryAccess()
2039 static std::string getReciprocalOpName(bool IsSqrt, EVT VT) { in getReciprocalOpName() argument
2040 std::string Name = VT.isVector() ? "vec-" : ""; in getReciprocalOpName()
2045 if (VT.getScalarType() == MVT::f64) { in getReciprocalOpName()
2048 assert(VT.getScalarType() == MVT::f32 && in getReciprocalOpName()
2082 static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override) { in getOpEnabled() argument
2115 std::string VTName = getReciprocalOpName(IsSqrt, VT); in getOpEnabled()
2142 static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override) { in getOpRefinementSteps() argument
2170 std::string VTName = getReciprocalOpName(IsSqrt, VT); in getOpRefinementSteps()
2188 int TargetLoweringBase::getRecipEstimateSqrtEnabled(EVT VT, in getRecipEstimateSqrtEnabled() argument
2190 return getOpEnabled(true, VT, getRecipEstimateForFunc(MF)); in getRecipEstimateSqrtEnabled()
2193 int TargetLoweringBase::getRecipEstimateDivEnabled(EVT VT, in getRecipEstimateDivEnabled() argument
2195 return getOpEnabled(false, VT, getRecipEstimateForFunc(MF)); in getRecipEstimateDivEnabled()
2198 int TargetLoweringBase::getSqrtRefinementSteps(EVT VT, in getSqrtRefinementSteps() argument
2200 return getOpRefinementSteps(true, VT, getRecipEstimateForFunc(MF)); in getSqrtRefinementSteps()
2203 int TargetLoweringBase::getDivRefinementSteps(EVT VT, in getDivRefinementSteps() argument
2205 return getOpRefinementSteps(false, VT, getRecipEstimateForFunc(MF)); in getDivRefinementSteps()