| 69e22d9f | 14-May-2021 |
Oleksij Rempel <[email protected]> |
MIPS: ath79: ar9331: add pause property for the MAC <> switch link
Both, MAC and switch support flow control, so add pause property for the
MAC <> switch link.
Signed-off-by: Oleksij Rempel <o.remp
MIPS: ath79: ar9331: add pause property for the MAC <> switch link
Both, MAC and switch support flow control, so add pause property for the
MAC <> switch link.
Signed-off-by: Oleksij Rempel <[email protected]>
Signed-off-by: Thomas Bogendoerfer <[email protected]>
show more ...
|
| 1e6a3492 | 17-Mar-2016 |
Antony Pavlov <[email protected]> |
MIPS: dts: qca: introduce AR9331 devicetree
This patch introduces devicetree for Atheros AR9331 SoC (AKA Hornet).
The AR9331 chip is a Wi-Fi System-On-Chip (WiSOC),
typically used in very cheap Acce
MIPS: dts: qca: introduce AR9331 devicetree
This patch introduces devicetree for Atheros AR9331 SoC (AKA Hornet).
The AR9331 chip is a Wi-Fi System-On-Chip (WiSOC),
typically used in very cheap Access Points and Routers.
Signed-off-by: Antony Pavlov <[email protected]>
Cc: Gabor Juhos <[email protected]>
Cc: Alban Bedel <[email protected]>
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/12878/
Signed-off-by: Ralf Baechle <[email protected]>
show more ...
|
| 3bdf1071 | 17-Mar-2016 |
Antony Pavlov <[email protected]> |
MIPS: ath79: update devicetree clock support for AR9132
Current ath79 clock.c code does not read reference clock and
pll setup from devicetree. E.g. you can set any clock rate value
in board DTS but
MIPS: ath79: update devicetree clock support for AR9132
Current ath79 clock.c code does not read reference clock and
pll setup from devicetree. E.g. you can set any clock rate value
in board DTS but it will have no effect on the real clk calculation.
This patch fixes some AR9132 devicetree clock support defects:
* clk initialization function ath79_clocks_init_dt_ng()
is introduced; it actually gets pll block base register
address and reference clock from devicetree;
* pll register parsing code is moved to the separate
ar724x_clk_init() function; this function
can be called from platform code or from devicetree code.
Also mips_hpt_frequency value is set from dt, so the appropriate
clock parameter is added to the cpu@0 devicetree node.
The same approach can be used for adding AR9331 devicetree support.
Signed-off-by: Antony Pavlov <[email protected]>
Cc: Gabor Juhos <[email protected]>
Cc: Alban Bedel <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/12876/
Signed-off-by: Ralf Baechle <[email protected]>
show more ...
|