1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_DRIVER_H 34 #define MLX5_DRIVER_H 35 36 #include <linux/kernel.h> 37 #include <linux/completion.h> 38 #include <linux/pci.h> 39 #include <linux/irq.h> 40 #include <linux/spinlock_types.h> 41 #include <linux/semaphore.h> 42 #include <linux/slab.h> 43 #include <linux/vmalloc.h> 44 #include <linux/radix-tree.h> 45 #include <linux/workqueue.h> 46 #include <linux/mempool.h> 47 #include <linux/interrupt.h> 48 #include <linux/idr.h> 49 50 #include <linux/mlx5/device.h> 51 #include <linux/mlx5/doorbell.h> 52 #include <linux/mlx5/srq.h> 53 #include <linux/timecounter.h> 54 #include <linux/ptp_clock_kernel.h> 55 56 enum { 57 MLX5_BOARD_ID_LEN = 64, 58 MLX5_MAX_NAME_LEN = 16, 59 }; 60 61 enum { 62 /* one minute for the sake of bringup. Generally, commands must always 63 * complete and we may need to increase this timeout value 64 */ 65 MLX5_CMD_TIMEOUT_MSEC = 60 * 1000, 66 MLX5_CMD_WQ_MAX_NAME = 32, 67 }; 68 69 enum { 70 CMD_OWNER_SW = 0x0, 71 CMD_OWNER_HW = 0x1, 72 CMD_STATUS_SUCCESS = 0, 73 }; 74 75 enum mlx5_sqp_t { 76 MLX5_SQP_SMI = 0, 77 MLX5_SQP_GSI = 1, 78 MLX5_SQP_IEEE_1588 = 2, 79 MLX5_SQP_SNIFFER = 3, 80 MLX5_SQP_SYNC_UMR = 4, 81 }; 82 83 enum { 84 MLX5_MAX_PORTS = 2, 85 }; 86 87 enum { 88 MLX5_EQ_VEC_PAGES = 0, 89 MLX5_EQ_VEC_CMD = 1, 90 MLX5_EQ_VEC_ASYNC = 2, 91 MLX5_EQ_VEC_PFAULT = 3, 92 MLX5_EQ_VEC_COMP_BASE, 93 }; 94 95 enum { 96 MLX5_MAX_IRQ_NAME = 32 97 }; 98 99 enum { 100 MLX5_ATOMIC_MODE_IB_COMP = 1 << 16, 101 MLX5_ATOMIC_MODE_CX = 2 << 16, 102 MLX5_ATOMIC_MODE_8B = 3 << 16, 103 MLX5_ATOMIC_MODE_16B = 4 << 16, 104 MLX5_ATOMIC_MODE_32B = 5 << 16, 105 MLX5_ATOMIC_MODE_64B = 6 << 16, 106 MLX5_ATOMIC_MODE_128B = 7 << 16, 107 MLX5_ATOMIC_MODE_256B = 8 << 16, 108 }; 109 110 enum { 111 MLX5_REG_QPTS = 0x4002, 112 MLX5_REG_QETCR = 0x4005, 113 MLX5_REG_QTCT = 0x400a, 114 MLX5_REG_QPDPM = 0x4013, 115 MLX5_REG_QCAM = 0x4019, 116 MLX5_REG_DCBX_PARAM = 0x4020, 117 MLX5_REG_DCBX_APP = 0x4021, 118 MLX5_REG_FPGA_CAP = 0x4022, 119 MLX5_REG_FPGA_CTRL = 0x4023, 120 MLX5_REG_FPGA_ACCESS_REG = 0x4024, 121 MLX5_REG_PCAP = 0x5001, 122 MLX5_REG_PMTU = 0x5003, 123 MLX5_REG_PTYS = 0x5004, 124 MLX5_REG_PAOS = 0x5006, 125 MLX5_REG_PFCC = 0x5007, 126 MLX5_REG_PPCNT = 0x5008, 127 MLX5_REG_PPTB = 0x500b, 128 MLX5_REG_PBMC = 0x500c, 129 MLX5_REG_PMAOS = 0x5012, 130 MLX5_REG_PUDE = 0x5009, 131 MLX5_REG_PMPE = 0x5010, 132 MLX5_REG_PELC = 0x500e, 133 MLX5_REG_PVLC = 0x500f, 134 MLX5_REG_PCMR = 0x5041, 135 MLX5_REG_PMLP = 0x5002, 136 MLX5_REG_PCAM = 0x507f, 137 MLX5_REG_NODE_DESC = 0x6001, 138 MLX5_REG_HOST_ENDIANNESS = 0x7004, 139 MLX5_REG_MCIA = 0x9014, 140 MLX5_REG_MLCR = 0x902b, 141 MLX5_REG_MPCNT = 0x9051, 142 MLX5_REG_MTPPS = 0x9053, 143 MLX5_REG_MTPPSE = 0x9054, 144 MLX5_REG_MCQI = 0x9061, 145 MLX5_REG_MCC = 0x9062, 146 MLX5_REG_MCDA = 0x9063, 147 MLX5_REG_MCAM = 0x907f, 148 }; 149 150 enum mlx5_qpts_trust_state { 151 MLX5_QPTS_TRUST_PCP = 1, 152 MLX5_QPTS_TRUST_DSCP = 2, 153 }; 154 155 enum mlx5_dcbx_oper_mode { 156 MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0, 157 MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3, 158 }; 159 160 enum mlx5_dct_atomic_mode { 161 MLX5_ATOMIC_MODE_DCT_OFF = 20, 162 MLX5_ATOMIC_MODE_DCT_NONE = 0 << MLX5_ATOMIC_MODE_DCT_OFF, 163 MLX5_ATOMIC_MODE_DCT_IB_COMP = 1 << MLX5_ATOMIC_MODE_DCT_OFF, 164 MLX5_ATOMIC_MODE_DCT_CX = 2 << MLX5_ATOMIC_MODE_DCT_OFF, 165 }; 166 167 enum { 168 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0, 169 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1, 170 }; 171 172 enum mlx5_page_fault_resume_flags { 173 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0, 174 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1, 175 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2, 176 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7, 177 }; 178 179 enum dbg_rsc_type { 180 MLX5_DBG_RSC_QP, 181 MLX5_DBG_RSC_EQ, 182 MLX5_DBG_RSC_CQ, 183 }; 184 185 enum port_state_policy { 186 MLX5_POLICY_DOWN = 0, 187 MLX5_POLICY_UP = 1, 188 MLX5_POLICY_FOLLOW = 2, 189 MLX5_POLICY_INVALID = 0xffffffff 190 }; 191 192 struct mlx5_field_desc { 193 struct dentry *dent; 194 int i; 195 }; 196 197 struct mlx5_rsc_debug { 198 struct mlx5_core_dev *dev; 199 void *object; 200 enum dbg_rsc_type type; 201 struct dentry *root; 202 struct mlx5_field_desc fields[0]; 203 }; 204 205 enum mlx5_dev_event { 206 MLX5_DEV_EVENT_SYS_ERROR, 207 MLX5_DEV_EVENT_PORT_UP, 208 MLX5_DEV_EVENT_PORT_DOWN, 209 MLX5_DEV_EVENT_PORT_INITIALIZED, 210 MLX5_DEV_EVENT_LID_CHANGE, 211 MLX5_DEV_EVENT_PKEY_CHANGE, 212 MLX5_DEV_EVENT_GUID_CHANGE, 213 MLX5_DEV_EVENT_CLIENT_REREG, 214 MLX5_DEV_EVENT_PPS, 215 MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT, 216 }; 217 218 enum mlx5_port_status { 219 MLX5_PORT_UP = 1, 220 MLX5_PORT_DOWN = 2, 221 }; 222 223 enum mlx5_eq_type { 224 MLX5_EQ_TYPE_COMP, 225 MLX5_EQ_TYPE_ASYNC, 226 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 227 MLX5_EQ_TYPE_PF, 228 #endif 229 }; 230 231 struct mlx5_bfreg_info { 232 u32 *sys_pages; 233 int num_low_latency_bfregs; 234 unsigned int *count; 235 236 /* 237 * protect bfreg allocation data structs 238 */ 239 struct mutex lock; 240 u32 ver; 241 bool lib_uar_4k; 242 u32 num_sys_pages; 243 u32 num_static_sys_pages; 244 u32 total_num_bfregs; 245 u32 num_dyn_bfregs; 246 }; 247 248 struct mlx5_cmd_first { 249 __be32 data[4]; 250 }; 251 252 struct mlx5_cmd_msg { 253 struct list_head list; 254 struct cmd_msg_cache *parent; 255 u32 len; 256 struct mlx5_cmd_first first; 257 struct mlx5_cmd_mailbox *next; 258 }; 259 260 struct mlx5_cmd_debug { 261 struct dentry *dbg_root; 262 struct dentry *dbg_in; 263 struct dentry *dbg_out; 264 struct dentry *dbg_outlen; 265 struct dentry *dbg_status; 266 struct dentry *dbg_run; 267 void *in_msg; 268 void *out_msg; 269 u8 status; 270 u16 inlen; 271 u16 outlen; 272 }; 273 274 struct cmd_msg_cache { 275 /* protect block chain allocations 276 */ 277 spinlock_t lock; 278 struct list_head head; 279 unsigned int max_inbox_size; 280 unsigned int num_ent; 281 }; 282 283 enum { 284 MLX5_NUM_COMMAND_CACHES = 5, 285 }; 286 287 struct mlx5_cmd_stats { 288 u64 sum; 289 u64 n; 290 struct dentry *root; 291 struct dentry *avg; 292 struct dentry *count; 293 /* protect command average calculations */ 294 spinlock_t lock; 295 }; 296 297 struct mlx5_cmd { 298 void *cmd_alloc_buf; 299 dma_addr_t alloc_dma; 300 int alloc_size; 301 void *cmd_buf; 302 dma_addr_t dma; 303 u16 cmdif_rev; 304 u8 log_sz; 305 u8 log_stride; 306 int max_reg_cmds; 307 int events; 308 u32 __iomem *vector; 309 310 /* protect command queue allocations 311 */ 312 spinlock_t alloc_lock; 313 314 /* protect token allocations 315 */ 316 spinlock_t token_lock; 317 u8 token; 318 unsigned long bitmask; 319 char wq_name[MLX5_CMD_WQ_MAX_NAME]; 320 struct workqueue_struct *wq; 321 struct semaphore sem; 322 struct semaphore pages_sem; 323 int mode; 324 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; 325 struct dma_pool *pool; 326 struct mlx5_cmd_debug dbg; 327 struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES]; 328 int checksum_disabled; 329 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; 330 }; 331 332 struct mlx5_port_caps { 333 int gid_table_len; 334 int pkey_table_len; 335 u8 ext_port_cap; 336 bool has_smi; 337 }; 338 339 struct mlx5_cmd_mailbox { 340 void *buf; 341 dma_addr_t dma; 342 struct mlx5_cmd_mailbox *next; 343 }; 344 345 struct mlx5_buf_list { 346 void *buf; 347 dma_addr_t map; 348 }; 349 350 struct mlx5_frag_buf { 351 struct mlx5_buf_list *frags; 352 int npages; 353 int size; 354 u8 page_shift; 355 }; 356 357 struct mlx5_frag_buf_ctrl { 358 struct mlx5_frag_buf frag_buf; 359 u32 sz_m1; 360 u32 frag_sz_m1; 361 u8 log_sz; 362 u8 log_stride; 363 u8 log_frag_strides; 364 }; 365 366 struct mlx5_eq_tasklet { 367 struct list_head list; 368 struct list_head process_list; 369 struct tasklet_struct task; 370 /* lock on completion tasklet list */ 371 spinlock_t lock; 372 }; 373 374 struct mlx5_eq_pagefault { 375 struct work_struct work; 376 /* Pagefaults lock */ 377 spinlock_t lock; 378 struct workqueue_struct *wq; 379 mempool_t *pool; 380 }; 381 382 struct mlx5_cq_table { 383 /* protect radix tree */ 384 spinlock_t lock; 385 struct radix_tree_root tree; 386 }; 387 388 struct mlx5_eq { 389 struct mlx5_core_dev *dev; 390 struct mlx5_cq_table cq_table; 391 __be32 __iomem *doorbell; 392 u32 cons_index; 393 struct mlx5_frag_buf buf; 394 int size; 395 unsigned int irqn; 396 u8 eqn; 397 int nent; 398 u64 mask; 399 struct list_head list; 400 int index; 401 struct mlx5_rsc_debug *dbg; 402 enum mlx5_eq_type type; 403 union { 404 struct mlx5_eq_tasklet tasklet_ctx; 405 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 406 struct mlx5_eq_pagefault pf_ctx; 407 #endif 408 }; 409 }; 410 411 struct mlx5_core_psv { 412 u32 psv_idx; 413 struct psv_layout { 414 u32 pd; 415 u16 syndrome; 416 u16 reserved; 417 u16 bg; 418 u16 app_tag; 419 u32 ref_tag; 420 } psv; 421 }; 422 423 struct mlx5_core_sig_ctx { 424 struct mlx5_core_psv psv_memory; 425 struct mlx5_core_psv psv_wire; 426 struct ib_sig_err err_item; 427 bool sig_status_checked; 428 bool sig_err_exists; 429 u32 sigerr_count; 430 }; 431 432 enum { 433 MLX5_MKEY_MR = 1, 434 MLX5_MKEY_MW, 435 }; 436 437 struct mlx5_core_mkey { 438 u64 iova; 439 u64 size; 440 u32 key; 441 u32 pd; 442 u32 type; 443 }; 444 445 #define MLX5_24BIT_MASK ((1 << 24) - 1) 446 447 enum mlx5_res_type { 448 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP, 449 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ, 450 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ, 451 MLX5_RES_SRQ = 3, 452 MLX5_RES_XSRQ = 4, 453 MLX5_RES_XRQ = 5, 454 MLX5_RES_DCT = MLX5_EVENT_QUEUE_TYPE_DCT, 455 }; 456 457 struct mlx5_core_rsc_common { 458 enum mlx5_res_type res; 459 atomic_t refcount; 460 struct completion free; 461 }; 462 463 struct mlx5_core_srq { 464 struct mlx5_core_rsc_common common; /* must be first */ 465 u32 srqn; 466 int max; 467 size_t max_gs; 468 size_t max_avail_gather; 469 int wqe_shift; 470 void (*event) (struct mlx5_core_srq *, enum mlx5_event); 471 472 atomic_t refcount; 473 struct completion free; 474 }; 475 476 struct mlx5_eq_table { 477 void __iomem *update_ci; 478 void __iomem *update_arm_ci; 479 struct list_head comp_eqs_list; 480 struct mlx5_eq pages_eq; 481 struct mlx5_eq async_eq; 482 struct mlx5_eq cmd_eq; 483 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 484 struct mlx5_eq pfault_eq; 485 #endif 486 int num_comp_vectors; 487 /* protect EQs list 488 */ 489 spinlock_t lock; 490 }; 491 492 struct mlx5_uars_page { 493 void __iomem *map; 494 bool wc; 495 u32 index; 496 struct list_head list; 497 unsigned int bfregs; 498 unsigned long *reg_bitmap; /* for non fast path bf regs */ 499 unsigned long *fp_bitmap; 500 unsigned int reg_avail; 501 unsigned int fp_avail; 502 struct kref ref_count; 503 struct mlx5_core_dev *mdev; 504 }; 505 506 struct mlx5_bfreg_head { 507 /* protect blue flame registers allocations */ 508 struct mutex lock; 509 struct list_head list; 510 }; 511 512 struct mlx5_bfreg_data { 513 struct mlx5_bfreg_head reg_head; 514 struct mlx5_bfreg_head wc_head; 515 }; 516 517 struct mlx5_sq_bfreg { 518 void __iomem *map; 519 struct mlx5_uars_page *up; 520 bool wc; 521 u32 index; 522 unsigned int offset; 523 }; 524 525 struct mlx5_core_health { 526 struct health_buffer __iomem *health; 527 __be32 __iomem *health_counter; 528 struct timer_list timer; 529 u32 prev; 530 int miss_counter; 531 bool sick; 532 /* wq spinlock to synchronize draining */ 533 spinlock_t wq_lock; 534 struct workqueue_struct *wq; 535 unsigned long flags; 536 struct work_struct work; 537 struct delayed_work recover_work; 538 }; 539 540 struct mlx5_qp_table { 541 /* protect radix tree 542 */ 543 spinlock_t lock; 544 struct radix_tree_root tree; 545 }; 546 547 struct mlx5_srq_table { 548 /* protect radix tree 549 */ 550 spinlock_t lock; 551 struct radix_tree_root tree; 552 }; 553 554 struct mlx5_mkey_table { 555 /* protect radix tree 556 */ 557 rwlock_t lock; 558 struct radix_tree_root tree; 559 }; 560 561 struct mlx5_vf_context { 562 int enabled; 563 u64 port_guid; 564 u64 node_guid; 565 enum port_state_policy policy; 566 }; 567 568 struct mlx5_core_sriov { 569 struct mlx5_vf_context *vfs_ctx; 570 int num_vfs; 571 int enabled_vfs; 572 }; 573 574 struct mlx5_irq_info { 575 cpumask_var_t mask; 576 char name[MLX5_MAX_IRQ_NAME]; 577 }; 578 579 struct mlx5_fc_stats { 580 struct rb_root counters; 581 struct list_head addlist; 582 /* protect addlist add/splice operations */ 583 spinlock_t addlist_lock; 584 585 struct workqueue_struct *wq; 586 struct delayed_work work; 587 unsigned long next_query; 588 unsigned long sampling_interval; /* jiffies */ 589 }; 590 591 struct mlx5_mpfs; 592 struct mlx5_eswitch; 593 struct mlx5_lag; 594 struct mlx5_pagefault; 595 596 struct mlx5_rate_limit { 597 u32 rate; 598 u32 max_burst_sz; 599 u16 typical_pkt_sz; 600 }; 601 602 struct mlx5_rl_entry { 603 struct mlx5_rate_limit rl; 604 u16 index; 605 u16 refcount; 606 }; 607 608 struct mlx5_rl_table { 609 /* protect rate limit table */ 610 struct mutex rl_lock; 611 u16 max_size; 612 u32 max_rate; 613 u32 min_rate; 614 struct mlx5_rl_entry *rl_entry; 615 }; 616 617 enum port_module_event_status_type { 618 MLX5_MODULE_STATUS_PLUGGED = 0x1, 619 MLX5_MODULE_STATUS_UNPLUGGED = 0x2, 620 MLX5_MODULE_STATUS_ERROR = 0x3, 621 MLX5_MODULE_STATUS_NUM = 0x3, 622 }; 623 624 enum port_module_event_error_type { 625 MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED, 626 MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE, 627 MLX5_MODULE_EVENT_ERROR_BUS_STUCK, 628 MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT, 629 MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST, 630 MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER, 631 MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE, 632 MLX5_MODULE_EVENT_ERROR_BAD_CABLE, 633 MLX5_MODULE_EVENT_ERROR_UNKNOWN, 634 MLX5_MODULE_EVENT_ERROR_NUM, 635 }; 636 637 struct mlx5_port_module_event_stats { 638 u64 status_counters[MLX5_MODULE_STATUS_NUM]; 639 u64 error_counters[MLX5_MODULE_EVENT_ERROR_NUM]; 640 }; 641 642 struct mlx5_priv { 643 char name[MLX5_MAX_NAME_LEN]; 644 struct mlx5_eq_table eq_table; 645 struct mlx5_irq_info *irq_info; 646 647 /* pages stuff */ 648 struct workqueue_struct *pg_wq; 649 struct rb_root page_root; 650 int fw_pages; 651 atomic_t reg_pages; 652 struct list_head free_list; 653 int vfs_pages; 654 655 struct mlx5_core_health health; 656 657 struct mlx5_srq_table srq_table; 658 659 /* start: qp staff */ 660 struct mlx5_qp_table qp_table; 661 struct dentry *qp_debugfs; 662 struct dentry *eq_debugfs; 663 struct dentry *cq_debugfs; 664 struct dentry *cmdif_debugfs; 665 /* end: qp staff */ 666 667 /* start: mkey staff */ 668 struct mlx5_mkey_table mkey_table; 669 /* end: mkey staff */ 670 671 /* start: alloc staff */ 672 /* protect buffer alocation according to numa node */ 673 struct mutex alloc_mutex; 674 int numa_node; 675 676 struct mutex pgdir_mutex; 677 struct list_head pgdir_list; 678 /* end: alloc staff */ 679 struct dentry *dbg_root; 680 681 /* protect mkey key part */ 682 spinlock_t mkey_lock; 683 u8 mkey_key; 684 685 struct list_head dev_list; 686 struct list_head ctx_list; 687 spinlock_t ctx_lock; 688 689 struct list_head waiting_events_list; 690 bool is_accum_events; 691 692 struct mlx5_flow_steering *steering; 693 struct mlx5_mpfs *mpfs; 694 struct mlx5_eswitch *eswitch; 695 struct mlx5_core_sriov sriov; 696 struct mlx5_lag *lag; 697 unsigned long pci_dev_data; 698 struct mlx5_fc_stats fc_stats; 699 struct mlx5_rl_table rl_table; 700 701 struct mlx5_port_module_event_stats pme_stats; 702 703 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 704 void (*pfault)(struct mlx5_core_dev *dev, 705 void *context, 706 struct mlx5_pagefault *pfault); 707 void *pfault_ctx; 708 struct srcu_struct pfault_srcu; 709 #endif 710 struct mlx5_bfreg_data bfregs; 711 struct mlx5_uars_page *uar; 712 }; 713 714 enum mlx5_device_state { 715 MLX5_DEVICE_STATE_UP, 716 MLX5_DEVICE_STATE_INTERNAL_ERROR, 717 }; 718 719 enum mlx5_interface_state { 720 MLX5_INTERFACE_STATE_UP = BIT(0), 721 }; 722 723 enum mlx5_pci_status { 724 MLX5_PCI_STATUS_DISABLED, 725 MLX5_PCI_STATUS_ENABLED, 726 }; 727 728 enum mlx5_pagefault_type_flags { 729 MLX5_PFAULT_REQUESTOR = 1 << 0, 730 MLX5_PFAULT_WRITE = 1 << 1, 731 MLX5_PFAULT_RDMA = 1 << 2, 732 }; 733 734 /* Contains the details of a pagefault. */ 735 struct mlx5_pagefault { 736 u32 bytes_committed; 737 u32 token; 738 u8 event_subtype; 739 u8 type; 740 union { 741 /* Initiator or send message responder pagefault details. */ 742 struct { 743 /* Received packet size, only valid for responders. */ 744 u32 packet_size; 745 /* 746 * Number of resource holding WQE, depends on type. 747 */ 748 u32 wq_num; 749 /* 750 * WQE index. Refers to either the send queue or 751 * receive queue, according to event_subtype. 752 */ 753 u16 wqe_index; 754 } wqe; 755 /* RDMA responder pagefault details */ 756 struct { 757 u32 r_key; 758 /* 759 * Received packet size, minimal size page fault 760 * resolution required for forward progress. 761 */ 762 u32 packet_size; 763 u32 rdma_op_len; 764 u64 rdma_va; 765 } rdma; 766 }; 767 768 struct mlx5_eq *eq; 769 struct work_struct work; 770 }; 771 772 struct mlx5_td { 773 struct list_head tirs_list; 774 u32 tdn; 775 }; 776 777 struct mlx5e_resources { 778 u32 pdn; 779 struct mlx5_td td; 780 struct mlx5_core_mkey mkey; 781 struct mlx5_sq_bfreg bfreg; 782 }; 783 784 #define MLX5_MAX_RESERVED_GIDS 8 785 786 struct mlx5_rsvd_gids { 787 unsigned int start; 788 unsigned int count; 789 struct ida ida; 790 }; 791 792 #define MAX_PIN_NUM 8 793 struct mlx5_pps { 794 u8 pin_caps[MAX_PIN_NUM]; 795 struct work_struct out_work; 796 u64 start[MAX_PIN_NUM]; 797 u8 enabled; 798 }; 799 800 struct mlx5_clock { 801 rwlock_t lock; 802 struct cyclecounter cycles; 803 struct timecounter tc; 804 struct hwtstamp_config hwtstamp_config; 805 u32 nominal_c_mult; 806 unsigned long overflow_period; 807 struct delayed_work overflow_work; 808 struct mlx5_core_dev *mdev; 809 struct ptp_clock *ptp; 810 struct ptp_clock_info ptp_info; 811 struct mlx5_pps pps_info; 812 }; 813 814 struct mlx5_core_dev { 815 struct pci_dev *pdev; 816 /* sync pci state */ 817 struct mutex pci_status_mutex; 818 enum mlx5_pci_status pci_status; 819 u8 rev_id; 820 char board_id[MLX5_BOARD_ID_LEN]; 821 struct mlx5_cmd cmd; 822 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; 823 struct { 824 u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 825 u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 826 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)]; 827 u32 mcam[MLX5_ST_SZ_DW(mcam_reg)]; 828 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)]; 829 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)]; 830 } caps; 831 phys_addr_t iseg_base; 832 struct mlx5_init_seg __iomem *iseg; 833 enum mlx5_device_state state; 834 /* sync interface state */ 835 struct mutex intf_state_mutex; 836 unsigned long intf_state; 837 void (*event) (struct mlx5_core_dev *dev, 838 enum mlx5_dev_event event, 839 unsigned long param); 840 struct mlx5_priv priv; 841 struct mlx5_profile *profile; 842 atomic_t num_qps; 843 u32 issi; 844 struct mlx5e_resources mlx5e_res; 845 struct { 846 struct mlx5_rsvd_gids reserved_gids; 847 u32 roce_en; 848 } roce; 849 #ifdef CONFIG_MLX5_FPGA 850 struct mlx5_fpga_device *fpga; 851 #endif 852 #ifdef CONFIG_RFS_ACCEL 853 struct cpu_rmap *rmap; 854 #endif 855 struct mlx5_clock clock; 856 struct mlx5_ib_clock_info *clock_info; 857 struct page *clock_info_page; 858 }; 859 860 struct mlx5_db { 861 __be32 *db; 862 union { 863 struct mlx5_db_pgdir *pgdir; 864 struct mlx5_ib_user_db_page *user_page; 865 } u; 866 dma_addr_t dma; 867 int index; 868 }; 869 870 enum { 871 MLX5_COMP_EQ_SIZE = 1024, 872 }; 873 874 enum { 875 MLX5_PTYS_IB = 1 << 0, 876 MLX5_PTYS_EN = 1 << 2, 877 }; 878 879 typedef void (*mlx5_cmd_cbk_t)(int status, void *context); 880 881 enum { 882 MLX5_CMD_ENT_STATE_PENDING_COMP, 883 }; 884 885 struct mlx5_cmd_work_ent { 886 unsigned long state; 887 struct mlx5_cmd_msg *in; 888 struct mlx5_cmd_msg *out; 889 void *uout; 890 int uout_size; 891 mlx5_cmd_cbk_t callback; 892 struct delayed_work cb_timeout_work; 893 void *context; 894 int idx; 895 struct completion done; 896 struct mlx5_cmd *cmd; 897 struct work_struct work; 898 struct mlx5_cmd_layout *lay; 899 int ret; 900 int page_queue; 901 u8 status; 902 u8 token; 903 u64 ts1; 904 u64 ts2; 905 u16 op; 906 bool polling; 907 }; 908 909 struct mlx5_pas { 910 u64 pa; 911 u8 log_sz; 912 }; 913 914 enum phy_port_state { 915 MLX5_AAA_111 916 }; 917 918 struct mlx5_hca_vport_context { 919 u32 field_select; 920 bool sm_virt_aware; 921 bool has_smi; 922 bool has_raw; 923 enum port_state_policy policy; 924 enum phy_port_state phys_state; 925 enum ib_port_state vport_state; 926 u8 port_physical_state; 927 u64 sys_image_guid; 928 u64 port_guid; 929 u64 node_guid; 930 u32 cap_mask1; 931 u32 cap_mask1_perm; 932 u32 cap_mask2; 933 u32 cap_mask2_perm; 934 u16 lid; 935 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */ 936 u8 lmc; 937 u8 subnet_timeout; 938 u16 sm_lid; 939 u8 sm_sl; 940 u16 qkey_violation_counter; 941 u16 pkey_violation_counter; 942 bool grh_required; 943 }; 944 945 static inline void *mlx5_buf_offset(struct mlx5_frag_buf *buf, int offset) 946 { 947 return buf->frags->buf + offset; 948 } 949 950 #define STRUCT_FIELD(header, field) \ 951 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ 952 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field 953 954 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) 955 { 956 return pci_get_drvdata(pdev); 957 } 958 959 extern struct dentry *mlx5_debugfs_root; 960 961 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) 962 { 963 return ioread32be(&dev->iseg->fw_rev) & 0xffff; 964 } 965 966 static inline u16 fw_rev_min(struct mlx5_core_dev *dev) 967 { 968 return ioread32be(&dev->iseg->fw_rev) >> 16; 969 } 970 971 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) 972 { 973 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; 974 } 975 976 static inline u16 cmdif_rev(struct mlx5_core_dev *dev) 977 { 978 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; 979 } 980 981 static inline u32 mlx5_base_mkey(const u32 key) 982 { 983 return key & 0xffffff00u; 984 } 985 986 static inline void mlx5_fill_fbc(u8 log_stride, u8 log_sz, 987 struct mlx5_frag_buf_ctrl *fbc) 988 { 989 fbc->log_stride = log_stride; 990 fbc->log_sz = log_sz; 991 fbc->sz_m1 = (1 << fbc->log_sz) - 1; 992 fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride; 993 fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1; 994 } 995 996 static inline void mlx5_core_init_cq_frag_buf(struct mlx5_frag_buf_ctrl *fbc, 997 void *cqc) 998 { 999 mlx5_fill_fbc(6 + MLX5_GET(cqc, cqc, cqe_sz), 1000 MLX5_GET(cqc, cqc, log_cq_size), 1001 fbc); 1002 } 1003 1004 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc, 1005 u32 ix) 1006 { 1007 unsigned int frag = (ix >> fbc->log_frag_strides); 1008 1009 return fbc->frag_buf.frags[frag].buf + 1010 ((fbc->frag_sz_m1 & ix) << fbc->log_stride); 1011 } 1012 1013 int mlx5_cmd_init(struct mlx5_core_dev *dev); 1014 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); 1015 void mlx5_cmd_use_events(struct mlx5_core_dev *dev); 1016 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); 1017 1018 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, 1019 int out_size); 1020 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size, 1021 void *out, int out_size, mlx5_cmd_cbk_t callback, 1022 void *context); 1023 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size, 1024 void *out, int out_size); 1025 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome); 1026 1027 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type); 1028 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); 1029 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); 1030 void mlx5_health_cleanup(struct mlx5_core_dev *dev); 1031 int mlx5_health_init(struct mlx5_core_dev *dev); 1032 void mlx5_start_health_poll(struct mlx5_core_dev *dev); 1033 void mlx5_stop_health_poll(struct mlx5_core_dev *dev); 1034 void mlx5_drain_health_wq(struct mlx5_core_dev *dev); 1035 void mlx5_trigger_health_work(struct mlx5_core_dev *dev); 1036 void mlx5_drain_health_recovery(struct mlx5_core_dev *dev); 1037 int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size, 1038 struct mlx5_frag_buf *buf, int node); 1039 int mlx5_buf_alloc(struct mlx5_core_dev *dev, 1040 int size, struct mlx5_frag_buf *buf); 1041 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); 1042 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size, 1043 struct mlx5_frag_buf *buf, int node); 1044 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); 1045 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev, 1046 gfp_t flags, int npages); 1047 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev, 1048 struct mlx5_cmd_mailbox *head); 1049 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 1050 struct mlx5_srq_attr *in); 1051 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq); 1052 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 1053 struct mlx5_srq_attr *out); 1054 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 1055 u16 lwm, int is_srq); 1056 void mlx5_init_mkey_table(struct mlx5_core_dev *dev); 1057 void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev); 1058 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev, 1059 struct mlx5_core_mkey *mkey, 1060 u32 *in, int inlen, 1061 u32 *out, int outlen, 1062 mlx5_cmd_cbk_t callback, void *context); 1063 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, 1064 struct mlx5_core_mkey *mkey, 1065 u32 *in, int inlen); 1066 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, 1067 struct mlx5_core_mkey *mkey); 1068 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey, 1069 u32 *out, int outlen); 1070 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *_mkey, 1071 u32 *mkey); 1072 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); 1073 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); 1074 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb, 1075 u16 opmod, u8 port); 1076 void mlx5_pagealloc_init(struct mlx5_core_dev *dev); 1077 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); 1078 int mlx5_pagealloc_start(struct mlx5_core_dev *dev); 1079 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); 1080 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, 1081 s32 npages); 1082 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); 1083 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); 1084 void mlx5_register_debugfs(void); 1085 void mlx5_unregister_debugfs(void); 1086 1087 void mlx5_fill_page_array(struct mlx5_frag_buf *buf, __be64 *pas); 1088 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas); 1089 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type); 1090 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type); 1091 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn); 1092 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, 1093 unsigned int *irqn); 1094 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 1095 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 1096 1097 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); 1098 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); 1099 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, 1100 int size_in, void *data_out, int size_out, 1101 u16 reg_num, int arg, int write); 1102 1103 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); 1104 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, 1105 int node); 1106 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); 1107 1108 const char *mlx5_command_str(int command); 1109 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); 1110 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); 1111 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, 1112 int npsvs, u32 *sig_index); 1113 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); 1114 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); 1115 int mlx5_query_odp_caps(struct mlx5_core_dev *dev, 1116 struct mlx5_odp_caps *odp_caps); 1117 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev, 1118 u8 port_num, void *out, size_t sz); 1119 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1120 int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 token, 1121 u32 wq_num, u8 type, int error); 1122 #endif 1123 1124 int mlx5_init_rl_table(struct mlx5_core_dev *dev); 1125 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev); 1126 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index, 1127 struct mlx5_rate_limit *rl); 1128 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl); 1129 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate); 1130 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0, 1131 struct mlx5_rate_limit *rl_1); 1132 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg, 1133 bool map_wc, bool fast_path); 1134 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg); 1135 1136 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev); 1137 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index, 1138 u8 roce_version, u8 roce_l3_type, const u8 *gid, 1139 const u8 *mac, bool vlan, u16 vlan_id, u8 port_num); 1140 1141 static inline int fw_initializing(struct mlx5_core_dev *dev) 1142 { 1143 return ioread32be(&dev->iseg->initializing) >> 31; 1144 } 1145 1146 static inline u32 mlx5_mkey_to_idx(u32 mkey) 1147 { 1148 return mkey >> 8; 1149 } 1150 1151 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) 1152 { 1153 return mkey_idx << 8; 1154 } 1155 1156 static inline u8 mlx5_mkey_variant(u32 mkey) 1157 { 1158 return mkey & 0xff; 1159 } 1160 1161 enum { 1162 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, 1163 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, 1164 }; 1165 1166 enum { 1167 MR_CACHE_LAST_STD_ENTRY = 20, 1168 MLX5_IMR_MTT_CACHE_ENTRY, 1169 MLX5_IMR_KSM_CACHE_ENTRY, 1170 MAX_MR_CACHE_ENTRIES 1171 }; 1172 1173 enum { 1174 MLX5_INTERFACE_PROTOCOL_IB = 0, 1175 MLX5_INTERFACE_PROTOCOL_ETH = 1, 1176 }; 1177 1178 struct mlx5_interface { 1179 void * (*add)(struct mlx5_core_dev *dev); 1180 void (*remove)(struct mlx5_core_dev *dev, void *context); 1181 int (*attach)(struct mlx5_core_dev *dev, void *context); 1182 void (*detach)(struct mlx5_core_dev *dev, void *context); 1183 void (*event)(struct mlx5_core_dev *dev, void *context, 1184 enum mlx5_dev_event event, unsigned long param); 1185 void (*pfault)(struct mlx5_core_dev *dev, 1186 void *context, 1187 struct mlx5_pagefault *pfault); 1188 void * (*get_dev)(void *context); 1189 int protocol; 1190 struct list_head list; 1191 }; 1192 1193 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol); 1194 int mlx5_register_interface(struct mlx5_interface *intf); 1195 void mlx5_unregister_interface(struct mlx5_interface *intf); 1196 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); 1197 1198 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev); 1199 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev); 1200 bool mlx5_lag_is_active(struct mlx5_core_dev *dev); 1201 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev); 1202 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev, 1203 u64 *values, 1204 int num_counters, 1205 size_t *offsets); 1206 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev); 1207 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up); 1208 1209 #ifndef CONFIG_MLX5_CORE_IPOIB 1210 static inline 1211 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev, 1212 struct ib_device *ibdev, 1213 const char *name, 1214 void (*setup)(struct net_device *)) 1215 { 1216 return ERR_PTR(-EOPNOTSUPP); 1217 } 1218 1219 static inline void mlx5_rdma_netdev_free(struct net_device *netdev) {} 1220 #else 1221 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev, 1222 struct ib_device *ibdev, 1223 const char *name, 1224 void (*setup)(struct net_device *)); 1225 void mlx5_rdma_netdev_free(struct net_device *netdev); 1226 #endif /* CONFIG_MLX5_CORE_IPOIB */ 1227 1228 struct mlx5_profile { 1229 u64 mask; 1230 u8 log_max_qp; 1231 struct { 1232 int size; 1233 int limit; 1234 } mr_cache[MAX_MR_CACHE_ENTRIES]; 1235 }; 1236 1237 enum { 1238 MLX5_PCI_DEV_IS_VF = 1 << 0, 1239 }; 1240 1241 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev) 1242 { 1243 return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF); 1244 } 1245 1246 #define MLX5_TOTAL_VPORTS(mdev) (1 + pci_sriov_get_totalvfs((mdev)->pdev)) 1247 #define MLX5_VPORT_MANAGER(mdev) \ 1248 (MLX5_CAP_GEN(mdev, vport_group_manager) && \ 1249 (MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && \ 1250 mlx5_core_is_pf(mdev)) 1251 1252 static inline int mlx5_get_gid_table_len(u16 param) 1253 { 1254 if (param > 4) { 1255 pr_warn("gid table length is zero\n"); 1256 return 0; 1257 } 1258 1259 return 8 * (1 << param); 1260 } 1261 1262 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev) 1263 { 1264 return !!(dev->priv.rl_table.max_size); 1265 } 1266 1267 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev) 1268 { 1269 return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) && 1270 MLX5_CAP_GEN(dev, num_vhca_ports) <= 1; 1271 } 1272 1273 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev) 1274 { 1275 return MLX5_CAP_GEN(dev, num_vhca_ports) > 1; 1276 } 1277 1278 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev) 1279 { 1280 return mlx5_core_is_mp_slave(dev) || 1281 mlx5_core_is_mp_master(dev); 1282 } 1283 1284 static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev) 1285 { 1286 if (!mlx5_core_mp_enabled(dev)) 1287 return 1; 1288 1289 return MLX5_CAP_GEN(dev, native_port_num); 1290 } 1291 1292 enum { 1293 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32, 1294 }; 1295 1296 static inline const struct cpumask * 1297 mlx5_get_vector_affinity_hint(struct mlx5_core_dev *dev, int vector) 1298 { 1299 return dev->priv.irq_info[vector].mask; 1300 } 1301 1302 #endif /* MLX5_DRIVER_H */ 1303