| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | InlineAsmLowering.cpp | 679 int64_t ExtVal = IsBool ? CI->getZExtValue() : CI->getSExtValue(); in lowerAsmOperandForConstraint() local
680 Ops.push_back(MachineOperand::CreateImm(ExtVal)); in lowerAsmOperandForConstraint()
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| H A D | LegalizerHelper.cpp | 3139 auto ExtVal = MIRBuilder.buildAnyExtOrTrunc(NewSrcTy, SrcReg); in lowerStore() local
3143 auto SmallVal = MIRBuilder.buildLShr(NewSrcTy, ExtVal, ShiftAmt); in lowerStore()
3156 MIRBuilder.buildStore(ExtVal, PtrReg, *LargeMMO); in lowerStore()
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| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.h | 77 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
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| H A D | WebAssemblyISelLowering.cpp | 803 bool WebAssemblyTargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const { in isVectorLoadExtDesirable()
804 EVT ExtT = ExtVal.getValueType(); in isVectorLoadExtDesirable()
805 EVT MemT = cast<LoadSDNode>(ExtVal->getOperand(0))->getValueType(0); in isVectorLoadExtDesirable()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | CodeGenPrepare.cpp | 2214 ZExtInst *ExtVal = dyn_cast<ZExtInst>(CI->getArgOperand(0)); in optimizeCallInst() local
2215 if (!ExtVal || !ExtVal->hasOneUse() || in optimizeCallInst()
2216 ExtVal->getParent() == CI->getParent()) in optimizeCallInst()
2219 ExtVal->moveBefore(CI); in optimizeCallInst()
2222 InsertedInsts.insert(ExtVal); in optimizeCallInst()
4318 Value *ExtVal = SExt; in promoteOperandForTruncAndAnyExt() local
4328 ExtVal = ZExt; in promoteOperandForTruncAndAnyExt()
4341 Instruction *ExtInst = dyn_cast<Instruction>(ExtVal); in promoteOperandForTruncAndAnyExt()
4348 return ExtVal; in promoteOperandForTruncAndAnyExt()
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| /llvm-project-15.0.7/llvm/unittests/Support/ |
| H A D | TargetParserTest.cpp | 1486 uint64_t ExtVal = 0; in TEST() local
1488 ExtVal |= Ext; in TEST()
1497 AArch64::getExtensionFeatures(ExtVal, Features); in TEST()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 462 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
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| H A D | ARMISelLowering.cpp | 19107 bool ARMTargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const { in isVectorLoadExtDesirable()
19108 EVT VT = ExtVal.getValueType(); in isVectorLoadExtDesirable()
19113 if (auto *Ld = dyn_cast<MaskedLoadSDNode>(ExtVal.getOperand(0))) { in isVectorLoadExtDesirable()
19125 if (ExtVal->use_empty() || in isVectorLoadExtDesirable()
19126 !ExtVal->use_begin()->isOnlyUserOf(ExtVal.getNode())) in isVectorLoadExtDesirable()
19129 SDNode *U = *ExtVal->use_begin(); in isVectorLoadExtDesirable()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 1110 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
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| H A D | AArch64ISelLowering.cpp | 4868 bool AArch64TargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const { in isVectorLoadExtDesirable()
4869 return ExtVal.getValueType().isScalableVector() || in isVectorLoadExtDesirable()
4871 ExtVal.getValueType(), in isVectorLoadExtDesirable()
14885 uint64_t ExtVal = C->getZExtValue(); in performSVEAndCombine() local
14890 if ((ExtVal == 0xFF && EltTy == MVT::i8) || in performSVEAndCombine()
14891 (ExtVal == 0xFFFF && EltTy == MVT::i16) || in performSVEAndCombine()
14892 (ExtVal == 0xFFFFFFFF && EltTy == MVT::i32)) in performSVEAndCombine()
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| /llvm-project-15.0.7/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 2424 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Val, in LowerSTOREVector() local
2427 ExtVal = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i16, ExtVal); in LowerSTOREVector()
2428 Ops.push_back(ExtVal); in LowerSTOREVector()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 2886 virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const { return false; } in isVectorLoadExtDesirable() argument
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 1977 SDValue ExtVal = SDValue(CurDAG->getMachineNode(PPC::INSERT_SUBREG, dl, in ExtendToInt64() local
1980 return ExtVal; in ExtendToInt64()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 5180 int64_t ExtVal = in LowerAsmOperandForConstraint() local
5183 DAG.getTargetConstant(Offset + ExtVal, SDLoc(C), MVT::i64)); in LowerAsmOperandForConstraint()
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| H A D | DAGCombiner.cpp | 13210 SDValue ExtVal = N0.getOperand(1); in visitTRUNCATE() local
13211 EVT ExtVT = cast<VTSDNode>(ExtVal)->getVT(); in visitTRUNCATE()
13214 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, TrX, ExtVal); in visitTRUNCATE()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 5733 SDValue ExtVal = DAG.getNode(ISD::BITCAST, SL, IntVT, in lowerINSERT_VECTOR_ELT() local
5737 SDValue LHS = DAG.getNode(ISD::AND, SL, IntVT, BFM, ExtVal); in lowerINSERT_VECTOR_ELT()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 34092 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const { in isVectorLoadExtDesirable()
34093 if (isa<MaskedLoadSDNode>(ExtVal.getOperand(0))) in isVectorLoadExtDesirable()
34096 EVT SrcVT = ExtVal.getOperand(0).getValueType(); in isVectorLoadExtDesirable()
55865 int64_t ExtVal = ExtOpc == ISD::ZERO_EXTEND ? CST->getZExtValue() in LowerAsmOperandForConstraint() local
55867 Result = DAG.getTargetConstant(ExtVal, SDLoc(Op), MVT::i64); in LowerAsmOperandForConstraint()
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