| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZShortenInst.cpp | 71 MI.tieOperands(0, 1); in tieOpsIfNeeded()
366 MI.tieOperands(0, 1); in processBlock()
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| H A D | SystemZPostRewrite.cpp | 217 MI.tieOperands(0, 1); in selectMI()
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| H A D | SystemZInstrInfo.cpp | 173 MI.tieOperands(0, 1); in expandRIEPseudo()
669 UseMI.tieOperands(0, 1); in FoldImmediate()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIShrinkInstructions.cpp | 341 MI.tieOperands( in shrinkMIMG()
498 MI.tieOperands(0, 2); in shrinkScalarLogicOp()
804 MI.tieOperands(0, 1); in runOnMachineFunction()
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| H A D | SIPeepholeSDWA.cpp | 485 MI.tieOperands(AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdst), in convertToSDWA()
1127 SDWAInst->tieOperands(PreserveDstIdx, SDWAInst->getNumOperands() - 1); in convertToSDWA()
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| H A D | AMDGPUInstructionSelector.cpp | 1797 MIB->tieOperands(0, MIB->getNumOperands() - 1); in selectImageIntrinsic()
1980 MovSDWA->tieOperands(0, MovSDWA->getNumOperands() - 1); in selectG_TRUNC()
2945 MovSDWA->tieOperands(0, MovSDWA->getNumOperands() - 1); in selectG_SHUFFLE_VECTOR()
2974 MovSDWA->tieOperands(0, MovSDWA->getNumOperands() - 1); in selectG_SHUFFLE_VECTOR()
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| H A D | SIInstrInfo.cpp | 922 MIB->tieOperands(0, MIB->getNumOperands() - 1); in copyPhysReg()
2020 MIB->tieOperands(ImpDefIdx, ImpUseIdx); in expandPostRAPseudo()
2054 MIB->tieOperands(ImpDefIdx, ImpUseIdx); in expandPostRAPseudo()
5398 Inst.tieOperands(NewVDst, NewVDstIn); in moveFlatAddrToVGPR()
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| H A D | SIISelLowering.cpp | 11944 MI.tieOperands(DstIdx, MI.getNumOperands() - 1); in AddIMGInit()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | InlineAsmLowering.cpp | 475 Inst->tieOperands(DefRegIdx, Inst->getNumOperands() - 1); in lowerInlineAsm()
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| H A D | Utils.cpp | 190 I.tieOperands(DefIdx, OpI); in constrainSelectedInstRegOperands()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | FixupStatepointCallerSaved.cpp | 533 MIB->tieOperands(NewIndices[OldDef], MIB->getNumOperands() - 1); in rewriteStatepoint()
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| H A D | MachineInstr.cpp | 264 tieOperands(DefIdx, OpNo); in addOperand()
1052 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) { in tieOperands() function in MachineInstr
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| H A D | TargetInstrInfo.cpp | 551 NewMI->tieOperands(TiedTo, NewMI->getNumOperands() - 1); in foldPatchpoint()
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| H A D | InlineSpiller.cpp | 888 MI->tieOperands(Tied.first, Tied.second); in foldMemoryOperand()
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| H A D | ModuloSchedule.cpp | 977 NewMI->tieOperands(i, UseIdx); in cloneInstr()
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| H A D | TargetLoweringBase.cpp | 1196 MIB->tieOperands(TiedTo, MIB->getNumOperands() - 1); in emitPatchPoint()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.cpp | 1140 MI->tieOperands(Def++, Use); in EmitMachineNode()
1311 MIB->tieOperands(DefIdx + j, UseIdx + j); in EmitSpecialNode()
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| /llvm-project-15.0.7/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 532 NewMI->tieOperands(0, NewMI->getNumOperands() - 1); in optimizeSelect()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterInfo.cpp | 672 MI.tieOperands(1, 3); in createScratchRegisterForInstruction()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ExpandPseudo.cpp | 580 MI.tieOperands(0, 1); in ExpandMI()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstr.h | 1508 void tieOperands(unsigned DefIdx, unsigned UseIdx);
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonExpandCondsets.cpp | 523 DefI->tieOperands(P.second, DefI->getNumOperands()-1); in updateDeadsInRange()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/MIRParser/ |
| H A D | MIParser.cpp | 1646 MI.tieOperands(TiedPair.first, TiedPair.second); in assignRegisterTies()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 2402 NewMI->tieOperands(0, NewMI->getNumOperands() - 1); in optimizeSelect()
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| H A D | ARMISelLowering.cpp | 12204 MI.tieOperands(DefIdx, i); in AdjustInstrPostInstrSelection()
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