| /llvm-project-15.0.7/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVPreLegalizer.cpp | 184 MRI.setRegClass(Reg, &SPIRV::IDRegClass); in propagateSPIRVType()
205 MRI.setRegClass(NewReg, RC); in insertAssignInstr()
216 MRI.setRegClass(Reg, &SPIRV::ANYIDRegClass); in insertAssignInstr()
321 MRI.setRegClass(IdReg, DstClass); in createNewIdReg()
371 MRI.setRegClass(DstReg, &SPIRV::IDRegClass); in processInstrsWithTypeFolding()
423 MRI.setRegClass(Dst, &SPIRV::IDRegClass); in processSwitches()
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| H A D | SPIRVCallLowering.cpp | 212 MRI->setRegClass(FuncVReg, &SPIRV::IDRegClass); in lowerFormalArguments()
232 MRI->setRegClass(VRegs[i][0], &SPIRV::IDRegClass); in lowerFormalArguments()
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| H A D | SPIRVGlobalRegistry.cpp | 64 MRI.setRegClass(Res, &SPIRV::TYPERegClass); in createTypeVReg()
70 MRI.setRegClass(Res, &SPIRV::TYPERegClass); in createTypeVReg()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | MachineRegisterInfo.cpp | 56 MachineRegisterInfo::setRegClass(Register Reg, const TargetRegisterClass *RC) { in setRegClass() function in MachineRegisterInfo
78 MRI.setRegClass(Reg, NewRC); in constrainRegClass()
140 setRegClass(Reg, NewRC); in recomputeRegClass()
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| H A D | RegisterBankInfo.cpp | 143 MRI.setRegClass(Reg, &RC); in constrainGenericRegister()
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| H A D | TailDuplicator.cpp | 423 MRI->setRegClass(VI->second.Reg, ConstrRC); in duplicateInstruction()
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| H A D | MachineLICM.cpp | 1363 MRI->setRegClass(Dup->getOperand(Defs[j]).getReg(), OrigRCs[j]); in EliminateCSE()
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| H A D | RegisterCoalescer.cpp | 1440 MRI->setRegClass(DstReg, NewRC); in reMaterializeTrivialDef()
2078 MRI->setRegClass(CP.getDstReg(), CP.getNewRC()); in joinCopy()
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| H A D | ModuloSchedule.cpp | 1899 MRI.setRegClass(R, MRI.getRegClass(PhiR)); in rewriteUsesOf()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | InstructionSelect.cpp | 178 MRI.setRegClass(SrcReg, DstRC); in runOnMachineFunction()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 412 MRI.setRegClass(Addr.Base.Reg, &PPC::G8RC_and_G8RC_NOX0RegClass); in PPCComputeAddress()
1315 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass); in SelectBinaryIntOp()
1319 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass); in SelectBinaryIntOp()
1332 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass); in SelectBinaryIntOp()
1341 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass); in SelectBinaryIntOp()
2428 MRI.setRegClass(Op0, &PPC::GPRC_and_GPRC_NOR0RegClass); in fastEmitInst_ri()
2430 MRI.setRegClass(Op0, &PPC::G8RC_and_G8RC_NOX0RegClass); in fastEmitInst_ri()
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| H A D | PPCMIPeephole.cpp | 970 MRI->setRegClass(DominatorReg, TRC); in simplifyCode()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIFixSGPRCopies.cpp | 207 MRI.setRegClass(DstReg, TRI->getEquivalentSGPRClass(MRI.getRegClass(DstReg))); in tryChangeVGPRtoSGPRinCopy()
259 MRI.setRegClass(DstReg, DstRC); in foldVGPRCopyIntoRegSequence()
839 MRI->setRegClass(PHIRes, TRI->getEquivalentAGPRClass(RC0)); in processPHINode()
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| H A D | SILowerI1Copies.cpp | 573 MRI->setRegClass(DstReg, IsWave32 ? &AMDGPU::SReg_32RegClass in lowerPhis()
703 MRI->setRegClass(DstReg, IsWave32 ? &AMDGPU::SReg_32RegClass in lowerCopiesToI1()
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| H A D | SIFoldOperands.cpp | 1681 MRI->setRegClass(DefReg, TRI->getEquivalentAGPRClass(RC)); in tryFoldLoad()
1683 MRI->setRegClass(DefReg, RC); in tryFoldLoad()
1689 MRI->setRegClass(Reg, TRI->getEquivalentAGPRClass(MRI->getRegClass(Reg))); in tryFoldLoad()
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| H A D | AMDGPUInstructionSelector.cpp | 171 MRI->setRegClass(SrcReg, SrcRC); in selectCOPY()
445 MRI->setRegClass(Dst1Reg, &AMDGPU::SReg_32RegClass); in selectG_UADDO_USUBO_UADDE_USUBE()
974 MRI->setRegClass(Reg, TRI.getWaveMaskRegClass()); in selectG_INTRINSIC()
1309 MRI->setRegClass(Reg, TRI.getWaveMaskRegClass()); in selectEndCfIntrinsic()
1870 MRI->setRegClass(CCReg, TRI.getConstrainedRegClassForOperand(CCOp, *MRI)); in selectG_SELECT()
2522 MRI->setRegClass(CondReg, ConstrainRC); in selectG_BRCOND()
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| H A D | AMDGPULegalizerInfo.cpp | 2509 B.getMRI()->setRegClass(PCReg, &AMDGPU::SReg_64RegClass); in buildPCRelGlobalAddress()
5596 MRI.setRegClass(Def, TRI->getWaveMaskRegClass()); in legalizeIntrinsic()
5597 MRI.setRegClass(Use, TRI->getWaveMaskRegClass()); in legalizeIntrinsic()
5632 MRI.setRegClass(Reg, TRI->getWaveMaskRegClass()); in legalizeIntrinsic()
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| H A D | SIISelLowering.cpp | 11983 MRI.setRegClass(Op.getReg(), NewRC); in AdjustInstrPostInstrSelection()
11992 MRI.setRegClass(Src2->getReg(), NewRC); in AdjustInstrPostInstrSelection()
11994 MRI.setRegClass(MI.getOperand(0).getReg(), NewRC); in AdjustInstrPostInstrSelection()
12424 MRI.setRegClass(Reg, TRI->getRegClass(NewClassID)); in finalizeLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrInfo.cpp | 1320 MRI.setRegClass(Reg, &SystemZ::FP32BitRegClass); in foldMemoryOperandImpl()
1322 MRI.setRegClass(Reg, &SystemZ::FP64BitRegClass); in foldMemoryOperandImpl()
1324 MRI.setRegClass(Reg, &SystemZ::VF128BitRegClass); in foldMemoryOperandImpl()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64LegalizerInfo.cpp | 957 MRI.setRegClass(ADRP.getReg(0), &AArch64::GPR64RegClass); in legalizeSmallCMGlobalValue()
979 MRI.setRegClass(ADRP.getReg(0), &AArch64::GPR64RegClass); in legalizeSmallCMGlobalValue()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86DomainReassignment.cpp | 508 MRI->setRegClass(Reg, getDstRC(MRI->getRegClass(Reg), Domain)); in reassign()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | MachineRegisterInfo.h | 681 void setRegClass(Register Reg, const TargetRegisterClass *RC);
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsInstructionSelector.cpp | 580 MRI.setRegClass(Dst, getRegClassForTypeOnBank(Dst, MRI)); in select()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/MIRParser/ |
| H A D | MIRParser.cpp | 673 MRI.setRegClass(Reg, Info.D.RC); in setupRegisterInfo()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.cpp | 660 MRI->setRegClass(NewVReg, SRC); in EmitRegSequence()
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