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Searched refs:isRegLoc (Results 1 – 25 of 31) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DCallingConvLower.cpp74 if (ValAssign.isRegLoc() && TRI.regsOverlap(ValAssign.getLocReg(), Reg)) in IsShadowAllocatedReg()
220 HaveRegParm = Locs.back().isRegLoc(); in getRemainingRegParmsForType()
226 if (Locs[I].isRegLoc()) in getRemainingRegParmsForType()
280 Loc1.isRegLoc() != Loc2.isRegLoc() || in resultsCompatible()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMCallLowering.cpp114 assert(VA.isRegLoc() && "Value shouldn't be assigned to reg"); in assignValueToReg()
152 assert(VA.isRegLoc() && "Value should be in reg"); in assignCustomValue()
153 assert(NextVA.isRegLoc() && "Value should be in reg"); in assignCustomValue()
285 assert(VA.isRegLoc() && "Value shouldn't be assigned to reg"); in assignValueToReg()
327 assert(VA.isRegLoc() && "Value should be in reg"); in assignCustomValue()
328 assert(NextVA.isRegLoc() && "Value should be in reg"); in assignCustomValue()
H A DARMFastISel.cpp1899 if (VA.isRegLoc() && !VA.needsCustom()) { in ProcessCallArgs()
1905 !VA.isRegLoc() || !ArgLocs[++i].isRegLoc()) in ProcessCallArgs()
1979 if (VA.isRegLoc() && !VA.needsCustom()) { in ProcessCallArgs()
1991 assert(VA.isRegLoc() && NextVA.isRegLoc() && in ProcessCallArgs()
2121 if (!VA.isRegLoc()) in SelectRet()
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp323 if (VA.isRegLoc()) { in LowerCall()
416 if (VA.isRegLoc()) { in lowerCallResult()
521 if (VA.isRegLoc()) { in LowerCallArguments()
673 if (VA.isRegLoc()) in LowerReturn()
701 if (!VA.isRegLoc()) in LowerReturn()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DCallingConvLower.h143 bool isRegLoc() const { return !isMem; } in isRegLoc() function
148 Register getLocReg() const { assert(isRegLoc()); return Loc; } in getLocReg()
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYISelLowering.cpp296 assert(VA.isRegLoc() && "Expected register VA assignment"); in unpack64()
350 else if (VA.isRegLoc()) in LowerFormalArguments()
447 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
453 assert(VA.isRegLoc() && "Expected return via registers"); in LowerReturn()
569 if (IsF64OnCSKY && VA.isRegLoc()) { in LowerCall()
602 if (VA.isRegLoc()) { in LowerCall()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp965 if (!ArgLoc.isRegLoc()) in parametersInCSRMatch()
1044 if (Loc1.isRegLoc() != Loc2.isRegLoc()) in resultsCompatible()
1047 if (Loc1.isRegLoc()) { in resultsCompatible()
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp321 if (VA.isRegLoc()) { in LowerFormalArguments()
442 if (VA.isRegLoc()) in LowerCall()
529 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp280 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn_32()
363 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn_64()
461 if (VA.isRegLoc()) { in LowerFormalArguments_32()
640 if (VA.isRegLoc()) { in LowerFormalArguments_64()
949 if (VA.isRegLoc()) { in LowerCall_32()
953 if (NextVA.isRegLoc()) { in LowerCall_32()
983 if (VA.isRegLoc()) { in LowerCall_32()
1081 assert(RVLocs[i].isRegLoc() && "Can only return in registers!"); in LowerCall_32()
1258 if (VA.isRegLoc()) { in LowerCall_64()
1293 if (i+1 < ArgLocs.size() && ArgLocs[i+1].isRegLoc() && in LowerCall_64()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp630 if (VA.isRegLoc()) { in LowerCall()
675 if (VA.isRegLoc()) in LowerCall()
898 if (VA.isRegLoc()) { in LowerFormalArguments()
1038 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
1213 if (!ArgLocs[i].isRegLoc()) in IsEligibleForTailCallOptimization()
1256 if (!VA.isRegLoc()) { in IsEligibleForTailCallOptimization()
1280 if (!VA.isRegLoc()) in IsEligibleForTailCallOptimization()
/llvm-project-15.0.7/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1066 if (VA.isRegLoc()) { in LowerCallResult()
1160 if (VA.isRegLoc()) { in LowerCCCCallTo()
1297 if (VA.isRegLoc()) { in LowerCCCArguments()
1468 if (VA.isRegLoc()) in LowerReturn()
1496 if (!VA.isRegLoc()) in LowerReturn()
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp454 if (VA.isRegLoc()) { in LowerCCCArguments()
560 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
690 if (VA.isRegLoc()) { in LowerCCCCallTo()
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp640 if (VA.isRegLoc()) { in LowerCCCArguments()
763 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
850 if (VA.isRegLoc()) { in LowerCCCCallTo()
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp967 if (VA.isRegLoc()) { in LowerCall()
1071 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp1399 !VA.isRegLoc() || VA.needsCustom()) in processCallArgs()
1507 assert(VA.isRegLoc() && "Can only return in registers!"); in finishCall()
1747 assert(VA.isRegLoc() && "Can only return in registers!"); in SelectRet()
H A DPPCISelLowering.cpp4065 if (VA.isRegLoc()) { in LowerFormalArguments_32SVR4()
5147 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerCallResult()
5881 if (VA.isRegLoc()) { in LowerCall_32SVR4()
7026 if (VA.isRegLoc()) { in LowerFormalArguments_AIX()
7077 assert(VA.isRegLoc() && "MemLocs should already be handled."); in LowerFormalArguments_AIX()
7119 for (; Offset != StackSize && ArgLocs[I].isRegLoc(); in LowerFormalArguments_AIX()
7141 if (VA.isRegLoc() && !VA.needsCustom()) { in LowerFormalArguments_AIX()
7392 if (VA.isRegLoc() && !VA.needsCustom()) { in LowerCall_AIX()
7413 assert(ArgLocs[I].isRegLoc() && ArgLocs[I].needsCustom() && in LowerCall_AIX()
7459 assert(VA.isRegLoc() && VA.needsCustom() && CFlags.IsVarArg && in LowerCall_AIX()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp1223 if (VA.isRegLoc() && !VA.needsCustom()) { in processCallArgs()
1714 if (!VA.isRegLoc()) in selectRet()
H A DMipsISelLowering.cpp3298 if (VA.isRegLoc()) { in LowerCall()
3354 if (VA.isRegLoc()) { in LowerCall()
3515 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerCallResult()
3664 bool IsRegLoc = VA.isRegLoc(); in LowerFormalArguments()
3844 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEISelLowering.cpp377 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
454 if (VA.isRegLoc()) { in LowerFormalArguments()
712 if (VA.isRegLoc()) { in LowerCall()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp785 if (ArgLoc.isRegLoc()) in areCalleeOutgoingArgsTailCallable()
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp1235 if (VA.isRegLoc()) { in LowerFormalArguments()
1558 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp520 if (VA.isRegLoc()) in LowerCall()
832 if (VA.isRegLoc() && ByVal && Flags.getByValSize() <= 8) in LowerFormalArguments()
835 bool InReg = VA.isRegLoc() && in LowerFormalArguments()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86FastISel.cpp1230 if (!VA.isRegLoc()) in X86SelectRet()
3383 if (VA.isRegLoc()) { in fastLowerCall()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp10750 assert(VA.isRegLoc() && "Expected register VA assignment"); in unpackF64OnRV32DSoftABI()
10978 else if (VA.isRegLoc()) in LowerFormalArguments()
11234 if (IsF64OnRV32DSoftABI && VA.isRegLoc()) { in LowerCall()
11318 if (VA.isRegLoc()) { in LowerCall()
11506 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
11510 assert(VA.isRegLoc() && "Expected return via registers"); in LowerReturn()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp1507 if (VA.isRegLoc()) { in LowerFormalArguments()
1650 if (!VA.isRegLoc()) in canUseSiblingCall()
1759 if (VA.isRegLoc()) { in LowerCall()
1973 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()

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