Lines Matching refs:isRegLoc

280     assert(VA.isRegLoc() && "Can only return in registers!");  in LowerReturn_32()
363     assert(VA.isRegLoc() && "Can only return in registers!");  in LowerReturn_64()
461     if (VA.isRegLoc()) {  in LowerFormalArguments_32()
640     if (VA.isRegLoc()) {  in LowerFormalArguments_64()
949       if (VA.isRegLoc()) {  in LowerCall_32()
953         if (NextVA.isRegLoc()) {  in LowerCall_32()
983     if (VA.isRegLoc()) {  in LowerCall_32()
1081     assert(RVLocs[i].isRegLoc() && "Can only return in registers!");  in LowerCall_32()
1146     if (!VA.isRegLoc() || (ValTy != MVT::f64 && ValTy != MVT::f128))  in fixupVariableFloatArgs()
1258     if (VA.isRegLoc()) {  in LowerCall_64()
1293         if (i+1 < ArgLocs.size() && ArgLocs[i+1].isRegLoc() &&  in LowerCall_64()
1397     assert(VA.isRegLoc() && "Can only return in registers!");  in LowerCall_64()