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Searched refs:getRegBank (Results 1 – 25 of 33) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64RegisterBankInfo.cpp55 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); in AArch64RegisterBankInfo()
60 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID); in AArch64RegisterBankInfo()
65 const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID); in AArch64RegisterBankInfo()
255 return getRegBank(AArch64::FPRRegBankID); in getRegBankFromRegClass()
277 return getRegBank(AArch64::GPRRegBankID); in getRegBankFromRegClass()
279 return getRegBank(AArch64::CCRegBankID); in getRegBankFromRegClass()
512 auto *RB = getRegBank(MI.getOperand(0).getReg(), MRI, TRI); in hasFPConstraints()
634 const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI); in getInstrMapping()
635 const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI); in getInstrMapping()
725 if (getRegBank(SrcReg, MRI, TRI) == &AArch64::FPRRegBank) in getInstrMapping()
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H A DAArch64InstructionSelector.cpp1082 assert(RBI.getRegBank(False, MRI, TRI)->getID() == in emitSelect()
1083 RBI.getRegBank(True, MRI, TRI)->getID() && in emitSelect()
1571 assert(RBI.getRegBank(CompareReg, MRI, TRI)->getID() == in emitCBZ()
2144 if (RBI.getRegBank(StoreSrcReg, MRI, TRI) == in contractCrossBankCopyIntoStore()
2145 RBI.getRegBank(DefDstReg, MRI, TRI)) in contractCrossBankCopyIntoStore()
2521 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); in select()
2826 const RegisterBank &RB = *RBI.getRegBank(ValReg, MRI, TRI); in select()
3208 assert((*RBI.getRegBank(DefReg, MRI, TRI)).getID() == in select()
4185 *RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI); in selectSplitVectorUnmerge()
4253 *RBI.getRegBank(SrcReg, MRI, TRI)); in selectUnmergeValues()
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/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp189 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI); in guessRegClass()
243 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectMergeValues()
248 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectMergeValues()
253 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectMergeValues()
275 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
518 if (RBI.getRegBank(Reg, MRI, TRI)->getID() != ExpectedRegBankID) { in validReg()
919 const auto &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in select()
920 const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in select()
1014 const auto &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in select()
1015 const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in select()
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H A DARMRegisterBankInfo.cpp141 const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID); in ARMRegisterBankInfo()
199 return getRegBank(ARM::GPRRegBankID); in getRegBankFromRegClass()
206 return getRegBank(ARM::FPRRegBankID); in getRegBankFromRegClass()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DRegisterBankInfo.h431 RegisterBank &getRegBank(unsigned ID) { in getRegBank() function
575 const RegisterBank &getRegBank(unsigned ID) const { in getRegBank() function
576 return const_cast<RegisterBankInfo *>(this)->getRegBank(ID); in getRegBank()
584 const RegisterBank *getRegBank(Register Reg, const MachineRegisterInfo &MRI,
/llvm-project-15.0.7/llvm/utils/TableGen/
H A DCodeGenTarget.h107 CodeGenRegBank &getRegBank() const;
126 return *getRegBank().getRegClass(R); in getRegisterClass()
H A DRegisterBankEmitter.cpp213 const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank(); in emitBaseClassImplementation()
277 const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank(); in run()
H A DDAGISelMatcherGen.cpp28 const CodeGenRegister *Reg = T.getRegBank().getReg(R); in getRegisterValueType()
30 for (const auto &RC : T.getRegBank().getRegClasses()) { in getRegisterValueType()
687 CGP.getTargetInfo().getRegBank().getReg(Def); in EmitResultLeafAsOperand()
733 const CodeGenRegBank &RB = CGP.getTargetInfo().getRegBank(); in EmitResultLeafAsOperand()
899 CGP.getTargetInfo().getRegBank().getReg(PhysRegInputs[i].first); in EmitResultInstructionAsOperand()
H A DCodeGenTarget.cpp355 CodeGenRegBank &CodeGenTarget::getRegBank() const { in getRegBank() function in CodeGenTarget
418 return getRegBank().getRegistersByName().lookup(Name); in getRegisterByName()
423 const CodeGenRegister *Reg = getRegBank().getReg(R); in getRegisterVTs()
425 for (const auto &RC : getRegBank().getRegClasses()) { in getRegisterVTs()
440 for (const auto &RC : getRegBank().getRegClasses()) in ReadLegalValueTypes()
H A DRegisterInfoEmitter.cpp62 CodeGenRegBank &RegBank = Target.getRegBank(); in RegisterInfoEmitter()
1068 BVE.add(Target.getRegBank().getReg(Reg)->EnumValue); in runMCDesc()
1705 CodeGenRegBank &RegBank = Target.getRegBank(); in run()
1723 CodeGenRegBank &RegBank = Target.getRegBank(); in debugDump()
H A DFastISelEmitter.cpp270 RC = Target.getRegBank().getRegClassForRegister(OpLeafRec); in initialize()
439 PhysReg += Target.getRegBank().getReg(OpLeafRec)->getName(); in PhyRegForNode()
H A DAsmMatcherEmitter.cpp1222 const auto &Registers = Target.getRegBank().getRegisters(); in buildRegisterClasses()
1223 auto &RegClassList = Target.getRegBank().getRegClasses(); in buildRegisterClasses()
2604 const auto &Regs = Target.getRegBank().getRegisters(); in emitMatchRegisterName()
2629 const auto &Regs = Target.getRegBank().getRegisters(); in emitMatchRegisterAltName()
H A DCodeGenInstruction.cpp587 .contains(T.getRegBank().getReg(ADI->getDef()))) in tryAliasOpMatch()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86RegisterBankInfo.cpp31 const RegisterBank &RBGPR = getRegBank(X86::GPRRegBankID); in X86RegisterBankInfo()
52 return getRegBank(X86::GPRRegBankID); in getRegBankFromRegClass()
59 return getRegBank(X86::VECRRegBankID); in getRegBankFromRegClass()
H A DX86InstructionSelector.cpp202 const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI); in getRegClass()
238 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectCopy()
242 const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in selectCopy()
512 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); in selectLoadStoreOp()
721 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in selectTruncOrPtrToInt()
722 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); in selectTruncOrPtrToInt()
850 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in selectAnyext()
851 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); in selectAnyext()
1325 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectMergeValues()
1394 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI); in materializeFP()
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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp287 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_AND_OR_XOR()
314 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_ADD_SUB()
504 const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, *MRI, TRI); in selectG_EXTRACT()
536 const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_MERGE_VALUES()
578 const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, *MRI, TRI); in selectG_UNMERGE_VALUES()
621 const RegisterBank *DstBank = RBI.getRegBank(Dst, *MRI, TRI); in selectG_BUILD_VECTOR_TRUNC()
1237 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectGroupStaticSize()
1927 const RegisterBank *SrcRB = RBI.getRegBank(SrcReg, *MRI, TRI); in selectG_TRUNC()
1934 DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_TRUNC()
2274 const RegisterBank *DstRB = RBI.getRegBank(Dst, *MRI, TRI); in selectG_FNEG()
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H A DAMDGPURegisterBankInfo.cpp648 const RegisterBank *Bank = getRegBank(Reg, *MRI, *TRI); in split64BitValueForMapping()
687 const RegisterBank *Bank = getRegBank(Src, MRI, *TRI); in buildReadFirstLane()
977 const RegisterBank *OpBank = getRegBank(Reg, MRI, *TRI); in collectWaterfallOperands()
1012 const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI); in constrainOpWithReadfirstlane()
3459 const RegisterBank *PtrBank = getRegBank(PtrReg, MRI, *TRI); in getValueMappingForPtr()
3478 const RegisterBank *PtrBank = getRegBank(PtrReg, MRI, *TRI); in getInstrMappingForLoad()
3514 const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI); in getRegBankID()
3622 const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI); in getInstrMapping()
3640 getValueMapping(0, Size, getRegBank(ResultBank)); in getInstrMapping()
3662 = getRegBank(MI.getOperand(0).getReg(), MRI, *TRI); in getInstrMapping()
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H A DAMDGPURegBankCombiner.cpp87 return RBI.getRegBank(Reg, MRI, TRI)->getID() == AMDGPU::VGPRRegBankID; in isVgprRegBank()
103 MRI.setRegBank(VgprReg, RBI.getRegBank(AMDGPU::VGPRRegBankID)); in getAsVgpr()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsRegisterBankInfo.cpp92 return getRegBank(Mips::GPRBRegBankID); in getRegBankFromRegClass()
101 return getRegBank(Mips::FPRBRegBankID); in getRegBankFromRegClass()
372 RBI.getRegBank(CopyInst->getOperand(Op).getReg(), MRI, TRI); in setTypesAccordingToPhysicalRegister()
702 MRI.setRegBank(Dest, getRegBank(Mips::GPRBRegBankID)); in setRegBank()
707 MRI.setRegBank(Dest, getRegBank(Mips::GPRBRegBankID)); in setRegBank()
H A DMipsInstructionSelector.cpp97 return RBI.getRegBank(Reg, MRI, TRI)->getID() == Mips::GPRBRegBankID; in isRegInGprb()
102 return RBI.getRegBank(Reg, MRI, TRI)->getID() == Mips::FPRBRegBankID; in isRegInFprb()
/llvm-project-15.0.7/llvm/lib/Target/M68k/GISel/
H A DM68kRegisterBankInfo.cpp64 return getRegBank(M68k::GPRRegBankID); in getRegBankFromRegClass()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DRegisterBankInfo.cpp69 const RegisterBank &RegBank = getRegBank(Idx); in verify()
80 RegisterBankInfo::getRegBank(Register Reg, const MachineRegisterInfo &MRI, in getRegBank() function in RegisterBankInfo
193 const RegisterBank *AltRegBank = getRegBank(Reg, MRI, TRI); in getInstrMappingImpl()
238 const RegisterBank *AltRegBank = getRegBank(Reg, MRI, TRI); in getInstrMappingImpl()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/MIRParser/
H A DMIParser.h149 const RegisterBank *getRegBank(StringRef Name);
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DRegBankSelect.cpp120 const RegisterBank *CurRegBank = RBI->getRegBank(Reg, *MRI, *TRI); in assignmentMatch()
243 const RegisterBank *CurRegBank = RBI->getRegBank(MO.getReg(), *MRI, *TRI); in getRepairCost()
634 RBI->getRegBank(MI.getOperand(1).getReg(), *MRI, *TRI); in assignInstr()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/
H A DCombinerHelper.h162 const RegisterBank *getRegBank(Register Reg) const;

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