125       const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, MRI, *RBI.TRI);  in applyBank()
151       const RegisterBank *DstBank = RBI.getRegBank(DstReg, MRI, *RBI.TRI);  in applyBank()
204     assert(&getRegBank(AMDGPU::SGPRRegBankID) == &AMDGPU::SGPRRegBank &&  in AMDGPURegisterBankInfo()
205            &getRegBank(AMDGPU::VGPRRegBankID) == &AMDGPU::VGPRRegBank &&  in AMDGPURegisterBankInfo()
206            &getRegBank(AMDGPU::AGPRRegBankID) == &AMDGPU::AGPRRegBank);  in AMDGPURegisterBankInfo()
648   const RegisterBank *Bank = getRegBank(Reg, *MRI, *TRI);  in split64BitValueForMapping()
687   const RegisterBank *Bank = getRegBank(Src, MRI, *TRI);  in buildReadFirstLane()
867       const RegisterBank *OpBank = getRegBank(OpReg, MRI, *TRI);  in executeInWaterfallLoop()
977     const RegisterBank *OpBank = getRegBank(Reg, MRI, *TRI);  in collectWaterfallOperands()
1012   const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI);  in constrainOpWithReadfirstlane()
1178   const RegisterBank *SizeBank = getRegBank(AllocSize, MRI, *TRI);  in applyMappingDynStackAlloc()
1278     if (RBI.getRegBank(Base, *MRI, *RBI.TRI) == &AMDGPU::VGPRRegBank) {  in setBufferOffsets()
1302     const RegisterBank *Src0Bank = RBI.getRegBank(Src0, *MRI, *RBI.TRI);  in setBufferOffsets()
1303     const RegisterBank *Src1Bank = RBI.getRegBank(Src1, *MRI, *RBI.TRI);  in setBufferOffsets()
1320   if (RBI.getRegBank(CombinedOffset, *MRI, *RBI.TRI) == &AMDGPU::VGPRRegBank) {  in setBufferOffsets()
2138         const RegisterBank *SrcBank = getRegBank(SrcReg, MRI, *TRI);  in applyMappingImpl()
2221     const RegisterBank *CondBank = getRegBank(CondRegs[0], MRI, *TRI);  in applyMappingImpl()
3318     if (const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI)) {  in getMappingType()
3335     if (const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI)) {  in isSALUMapping()
3459   const RegisterBank *PtrBank = getRegBank(PtrReg, MRI, *TRI);  in getValueMappingForPtr()
3478   const RegisterBank *PtrBank = getRegBank(PtrReg, MRI, *TRI);  in getInstrMappingForLoad()
3514   const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI);  in getRegBankID()
3562     const RegisterBank *DstBank = getRegBank(MI.getOperand(0).getReg(), MRI,  in getInstrMapping()
3564     const RegisterBank *SrcBank = getRegBank(MI.getOperand(1).getReg(), MRI,  in getInstrMapping()
3602     const ValueMapping &ValMap = getValueMapping(0, Size, getRegBank(BankID));  in getInstrMapping()
3617     if (const RegisterBank *DstBank = getRegBank(DstReg, MRI, *TRI))  in getInstrMapping()
3622       const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI);  in getInstrMapping()
3640         getValueMapping(0, Size, getRegBank(ResultBank));  in getInstrMapping()
3662         = getRegBank(MI.getOperand(0).getReg(), MRI, *TRI);  in getInstrMapping()
3807       if (const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI)) {  in getInstrMapping()
3975     const RegisterBank *SrcBank = getRegBank(Src, MRI, *TRI);  in getInstrMapping()