731     const RegisterBank *OpBank = RBI.getRegBank(MO.getReg(), MRI, TRI);  in unsupportedBinOp()
890   const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI);  in getRegClassesForCopy()
891   const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI);  in getRegClassesForCopy()
915   const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI);  in selectCopy()
916   const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI);  in selectCopy()
1082   assert(RBI.getRegBank(False, MRI, TRI)->getID() ==  in emitSelect()
1083              RBI.getRegBank(True, MRI, TRI)->getID() &&  in emitSelect()
1092   if (RBI.getRegBank(True, MRI, TRI)->getID() != AArch64::GPRRegBankID) {  in emitSelect()
1571   assert(RBI.getRegBank(CompareReg, MRI, TRI)->getID() ==  in emitCBZ()
1854       getRegClassForTypeOnBank(Ty, RBI.getRegBank(AArch64::FPRRegBankID));  in selectVectorAshrLshr()
2017     if (RBI.getRegBank(SrcReg, MRI, TRI)->getID() == AArch64::FPRRegBankID) {  in preISelLower()
2053     MRI.setRegBank(PtrToInt.getReg(0), RBI.getRegBank(AArch64::FPRRegBankID));  in convertPtrAddToAdd()
2055     MRI.setRegBank(PtrToInt.getReg(0), RBI.getRegBank(AArch64::GPRRegBankID));  in convertPtrAddToAdd()
2144   if (RBI.getRegBank(StoreSrcReg, MRI, TRI) ==  in contractCrossBankCopyIntoStore()
2145       RBI.getRegBank(DefDstReg, MRI, TRI))  in contractCrossBankCopyIntoStore()
2521     const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);  in select()
2642       const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI);  in select()
2643       const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);  in select()
2816     const RegisterBank &PtrRB = *RBI.getRegBank(PtrReg, MRI, TRI);  in select()
2826     const RegisterBank &RB = *RBI.getRegBank(ValReg, MRI, TRI);  in select()
2950     const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);  in select()
2996         MRI.setRegBank(Trunc.getReg(0), RBI.getRegBank(AArch64::GPRRegBankID));  in select()
3009     const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);  in select()
3069     const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);  in select()
3070     const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI);  in select()
3145     const RegisterBank &RBDst = *RBI.getRegBank(DstReg, MRI, TRI);  in select()
3152     const RegisterBank &RBSrc = *RBI.getRegBank(SrcReg, MRI, TRI);  in select()
3208     assert((*RBI.getRegBank(DefReg, MRI, TRI)).getID() ==  in select()
3223           RBI.getRegBank(SrcReg, MRI, TRI)->getID() == AArch64::GPRRegBankID;  in select()
3403     const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);  in select()
3432     if (RBI.getRegBank(I.getOperand(1).getReg(), MRI, TRI)->getID() !=  in select()
3915   const RegisterBank &VecRB = *RBI.getRegBank(SrcReg, MRI, TRI);  in selectVectorICmp()
3978   const RegisterBank &RB = *RBI.getRegBank(I.getOperand(1).getReg(), MRI, TRI);  in selectMergeValues()
4089   const RegisterBank &VecRB = *RBI.getRegBank(VecReg, MRI, TRI);  in emitExtractVectorElt()
4147   if (RBI.getRegBank(DstReg, MRI, TRI)->getID() != AArch64::FPRRegBankID) {  in selectExtractElt()
4159   const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);  in selectExtractElt()
4185       *RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI);  in selectSplitVectorUnmerge()
4203   if (RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI)->getID() !=  in selectUnmergeValues()
4205       RBI.getRegBank(I.getOperand(1).getReg(), MRI, TRI)->getID() !=  in selectUnmergeValues()
4253         *RBI.getRegBank(SrcReg, MRI, TRI));  in selectUnmergeValues()
4677   const RegisterBank &FPRBank = *RBI.getRegBank(Op1, MRI, TRI);  in emitVectorConcat()
5328   const RegisterBank &EltRB = *RBI.getRegBank(EltReg, MRI, TRI);  in selectInsertElt()
5351         getRegClassForTypeOnBank(DstTy, *RBI.getRegBank(DemoteVec, MRI, TRI));  in selectInsertElt()
5457   const RegisterBank &EltRB = *RBI.getRegBank(EltReg, MRI, TRI);  in tryOptBuildVecToSubregToReg()
5458   const RegisterBank &DstRB = *RBI.getRegBank(Dst, MRI, TRI);  in tryOptBuildVecToSubregToReg()
5502   const RegisterBank &RB = *RBI.getRegBank(I.getOperand(1).getReg(), MRI, TRI);  in selectBuildVector()
5530         getRegClassForTypeOnBank(DstTy, *RBI.getRegBank(DstVec, MRI, TRI));  in selectBuildVector()
5763     if (RBI.getRegBank(SrcReg, MRI, TRI)->getID() != AArch64::FPRRegBankID) {  in selectIntrinsic()
5772     if (RBI.getRegBank(DstReg, MRI, TRI)->getID() != AArch64::FPRRegBankID)  in selectIntrinsic()