| /llvm-project-15.0.7/llvm/tools/llvm-tapi-diff/ |
| H A D | DiffEngine.h | 73 InterfaceInputOrder getOrder() const { return Order; } in getOrder() function
96 InterfaceInputOrder getOrder() const { return Order; } in getOrder() function
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| H A D | DiffEngine.cpp | 445 return ValA.getOrder() < ValB.getOrder(); in sortTargetValues()
448 return ValA.getOrder() == ValB.getOrder() && ValA.getVal() < ValB.getVal(); in sortTargetValues()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGSDNodes.cpp | 755 unsigned DVOrder = DV->getOrder(); in ProcessSDDbgValues()
966 return LHS->getOrder() < RHS->getOrder(); in EmitSchedule()
979 if ((*DI)->getOrder() < LastOrder || (*DI)->getOrder() >= Order) in EmitSchedule()
1005 assert((*DI)->getOrder() >= LastOrder && in EmitSchedule()
1027 (*DLI)->getOrder() >= LastOrder && (*DLI)->getOrder() < Order; in EmitSchedule()
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| H A D | SDNodeDbgValue.h | 219 unsigned getOrder() const { return Order; } in getOrder() function
259 unsigned getOrder() const { return Order; } in getOrder() function
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| H A D | SelectionDAGDumper.cpp | 851 OS << " DbgVal(Order=" << getOrder() << ')'; in print()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | AllocationOrder.cpp | 34 auto Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); in create()
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| H A D | AllocationOrder.h | 111 ArrayRef<MCPhysReg> getOrder() const { return Order; } in getOrder() function
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| H A D | RegAllocBase.cpp | 128 ArrayRef<MCPhysReg> AllocOrder = RegClassInfo.getOrder(RC); in allocatePhysRegs()
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| H A D | RegAllocFast.cpp | 799 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in allocVirtReg()
852 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in allocVirtRegUndef()
983 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in useVirtReg()
1225 unsigned ClassSize0 = RegClassInfo.getOrder(&RC0).size(); in allocateInstruction()
1226 unsigned ClassSize1 = RegClassInfo.getOrder(&RC1).size(); in allocateInstruction()
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| H A D | BreakFalseDeps.cpp | 155 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC); in pickBestRegisterForUndef()
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| H A D | CriticalAntiDepBreaker.cpp | 406 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC); in findSuitableFreeRegister()
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| H A D | AggressiveAntiDepBreaker.cpp | 618 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC); in FindSuitableFreeRegisters()
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| H A D | RegAllocGreedy.cpp | 500 unsigned OrderLimit = Order.getOrder().size(); in getOrderLimit()
514 if (RegCosts[Order.getOrder().back()] >= CostPerUseLimit) { in getOrderLimit()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | RegisterClassInfo.h | 102 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder() function
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| /llvm-project-15.0.7/llvm/utils/TableGen/ |
| H A D | RegisterInfoEmitter.cpp | 1048 ArrayRef<Record*> Order = RC.getOrder(); in runMCDesc()
1084 ArrayRef<Record *> Order = RC.getOrder(); in runMCDesc()
1093 << RegClassStrings.get(RC.getName()) << ", " << RC.getOrder().size() in runMCDesc()
1242 ArrayRef<Record*> Order = RC.getOrder(); in runTargetDesc()
1393 ArrayRef<Record*> Elems = RC.getOrder(oi); in runTargetDesc()
1406 if (RC.getOrder(oi).empty()) in runTargetDesc()
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| H A D | CodeGenRegisters.h | 427 ArrayRef<Record*> getOrder(unsigned No = 0) const {
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| H A D | AsmMatcherEmitter.cpp | 1233 RegisterSet(RC.getOrder().begin(), RC.getOrder().end())); in buildRegisterClasses()
1309 ClassInfo *CI = RegisterSetClasses[RegisterSet(RC.getOrder().begin(), in buildRegisterClasses()
1310 RC.getOrder().end())]; in buildRegisterClasses()
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| /llvm-project-15.0.7/llvm/include/llvm/Passes/ |
| H A D | StandardInstrumentations.h | 292 std::vector<std::string> &getOrder() { return Order; } in getOrder() function
293 const std::vector<std::string> &getOrder() const { return Order; } in getOrder() function
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIPreAllocateWWMRegs.cpp | 103 for (MCRegister PhysReg : RegClassInfo.getOrder(MRI->getRegClass(Reg))) { in processDef()
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| /llvm-project-15.0.7/llvm/lib/Passes/ |
| H A D | StandardInstrumentations.cpp | 576 std::vector<std::string>::const_iterator BI = Before.getOrder().begin(); in report()
577 std::vector<std::string>::const_iterator BE = Before.getOrder().end(); in report()
578 std::vector<std::string>::const_iterator AI = After.getOrder().begin(); in report()
579 std::vector<std::string>::const_iterator AE = After.getOrder().end(); in report()
691 FD.getOrder().emplace_back(B.getName()); in generateFunctionData()
694 Data.getOrder().emplace_back(F.getName()); in generateFunctionData()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64A57FPLoadBalancing.cpp | 519 auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID)); in scavengeRegister()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMLowOverheadLoops.cpp | 128 const SmallVectorImpl<MachineBasicBlock*> &getOrder() const { in getOrder() function in __anon59c8a0920111::PostOrderLoopTraversal
1806 const SmallVectorImpl<MachineBasicBlock*> &PostOrder = DFS.getOrder(); in Expand()
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| /llvm-project-15.0.7/clang/lib/CodeGen/ |
| H A D | CGOpenMPRuntime.h | 553 unsigned getOrder() const { return Order; } in getOrder() function
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| H A D | CGOpenMPRuntime.cpp | 3151 GetMDInt(Line), GetMDInt(E.getOrder())}; in createOffloadEntriesAndInfoMetadata()
3165 OrderedEntries[E.getOrder()] = std::make_tuple(&E, Loc, ParentName); in createOffloadEntriesAndInfoMetadata()
3166 ParentFunctions[E.getOrder()] = ParentName; in createOffloadEntriesAndInfoMetadata()
3190 GetMDInt(E.getFlags()), GetMDInt(E.getOrder())}; in createOffloadEntriesAndInfoMetadata()
3193 OrderedEntries[E.getOrder()] = in createOffloadEntriesAndInfoMetadata()
3210 StringRef FnName = ParentFunctions[CE->getOrder()]; in createOffloadEntriesAndInfoMetadata()
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| H A D | CGAtomic.cpp | 850 llvm::Value *Order = EmitScalarExpr(E->getOrder()); in EmitAtomicExpr()
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