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Searched refs:getOperandConstraint (Results 1 – 23 of 23) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/
H A DX86BaseInfo.h1064 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0) in getOperandBias()
1069 Desc.getOperandConstraint(6, MCOI::TIED_TO) == 0) in getOperandBias()
1074 if (NumOps >= 4 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 && in getOperandBias()
1075 Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1) in getOperandBias()
1079 if (NumOps == 9 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 && in getOperandBias()
1080 (Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1 || in getOperandBias()
1081 Desc.getOperandConstraint(8, MCOI::TIED_TO) == 1)) in getOperandBias()
H A DX86InstComments.cpp271 if (Desc.getOperandConstraint(MaskOp, MCOI::TIED_TO) != -1) in printMasking()
/llvm-project-15.0.7/llvm/include/llvm/MC/
H A DMCInstrDesc.h212 int getOperandConstraint(unsigned OpNum, in getOperandConstraint() function
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZHazardRecognizer.cpp127 MID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) in has4RegOps()
H A DSystemZShortenInst.cpp69 if (MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) == 0 && in tieOpsIfNeeded()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGSDNodes.cpp213 if (MCID.getOperandConstraint(I, MCOI::TIED_TO) != -1) in ClusterNeighboringLoads()
451 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { in AddSchedEdges()
H A DScheduleDAGFast.cpp252 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { in CopyAndMoveSuccessors()
H A DScheduleDAGRRList.cpp1036 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { in TryUnfoldSU()
2839 if (MCID.getOperandConstraint(i+NumRes, MCOI::TIED_TO) != -1) { in canClobber()
3084 if (MCID.getOperandConstraint(j+NumRes, MCOI::TIED_TO) == -1) in AddPseudoTwoAddrDeps()
H A DInstrEmitter.cpp360 bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1; in AddRegisterOperand()
/llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/
H A DMCInstrDescView.cpp121 int TiedToIndex = Description->getOperandConstraint(OpIndex, MCOI::TIED_TO); in create()
/llvm-project-15.0.7/bolt/lib/Passes/
H A DRegReAssign.cpp173 if (Desc.getOperandConstraint(I, MCOI::TIED_TO) != -1) in rankRegisters()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DMachineInstr.cpp262 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO); in addOperand()
267 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1) in addOperand()
1451 int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO); in hasComplexRegisterTies()
H A DTargetInstrInfo.cpp205 MI.getDesc().getOperandConstraint(Idx1, MCOI::TIED_TO) == 0) { in commuteInstructionImpl()
210 MI.getDesc().getOperandConstraint(Idx2, MCOI::TIED_TO) == 0) { in commuteInstructionImpl()
H A DMachineVerifier.cpp1936 int TiedTo = MCID.getOperandConstraint(MONum, MCOI::TIED_TO); in visitMachineOperand()
1993 if (-1 == MCID.getOperandConstraint(OtherIdx, MCOI::TIED_TO)) in visitMachineOperand()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp188 int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO); in constrainSelectedInstRegOperands()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp3512 Desc.getOperandConstraint(DstIdx, MCOI::EARLY_CLOBBER) == -1) { in validateEarlyClobberLimitations()
8076 && Desc.getOperandConstraint(OpNum + 1, MCOI::OperandConstraint::TIED_TO) == -1; in isRegOrImmWithInputMods()
8785 auto TiedTo = Desc.getOperandConstraint(Inst.getNumOperands(), in cvtVOP3DPP()
8855 auto TiedTo = Desc.getOperandConstraint(Inst.getNumOperands(), in cvtDPP()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp685 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx, in getInstruction()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp2607 if ((MI.getDesc().getOperandConstraint(Desc.getNumDefs(), in findCommutedOpIndices()
6066 NumOps > 1 && MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1; in foldMemoryOperandImpl()
6176 0 == MI.getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO); in foldMemoryOperandImpl()
6178 0 == MI.getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO); in foldMemoryOperandImpl()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp1183 assert(MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) && in commuteInstructionImpl()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp4693 (MCID.getOperandConstraint(i, MCOI::TIED_TO) == -1) && in validateInstruction()
/llvm-project-15.0.7/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1022 int TiedOp = ARMInsts[MI.getOpcode()].getOperandConstraint( in AddThumbPredicate()
/llvm-project-15.0.7/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp2507 int TiedOp = MCID.getOperandConstraint(NextOpIndex, MCOI::TIED_TO); in addVPTPredROperands()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp12202 int DefIdx = MCID->getOperandConstraint(i, MCOI::TIED_TO); in AdjustInstrPostInstrSelection()