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Searched refs:TmpReg (Results 1 – 25 of 44) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVERegisterInfo.cpp307 Register TmpReg = VE::SX16; in processSTVM() local
312 TmpReg, getKillRegState(true)); in processSTVM()
344 unsigned TmpReg = VE::SX16; in processLDVM() local
363 .addReg(TmpReg, getKillRegState(true)) in processLDVM()
387 Register TmpReg = VE::SX16; in processSTVM512() local
394 TmpReg, getKillRegState(true)); in processSTVM512()
405 TmpReg, getKillRegState(true)); in processSTVM512()
432 Register TmpReg = VE::SX16; in processLDVM512() local
440 .addReg(TmpReg, getKillRegState(true)) in processLDVM512()
450 .addReg(TmpReg, getKillRegState(true)) in processLDVM512()
[all …]
H A DVEInstrInfo.cpp376 Register TmpReg = VE::SX16; in copyPhysReg() local
377 Register SubTmp = TRI->getSubReg(TmpReg, VE::sub_i32); in copyPhysReg()
378 BuildMI(MBB, I, DL, get(VE::LEAzii), TmpReg) in copyPhysReg()
386 MIB.getInstr()->addRegisterKilled(TmpReg, TRI, true); in copyPhysReg()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SpeculationHardening.cpp161 unsigned TmpReg) const;
307 Register TmpReg = RS.FindUnusedReg(&AArch64::GPR64commonRegClass); in instrumentControlFlow() local
310 if (TmpReg != 0) dbgs() << printReg(TmpReg, TRI) << " "; in instrumentControlFlow()
312 if (TmpReg == 0) in instrumentControlFlow()
315 ReturnInstructions.push_back({&MI, TmpReg}); in instrumentControlFlow()
317 CallInstructions.push_back({&MI, TmpReg}); in instrumentControlFlow()
384 unsigned TmpReg) const { in insertRegToSPTaintPropagation()
393 .addDef(TmpReg) in insertRegToSPTaintPropagation()
399 .addDef(TmpReg, RegState::Renamable) in insertRegToSPTaintPropagation()
400 .addUse(TmpReg, RegState::Kill | RegState::Renamable) in insertRegToSPTaintPropagation()
[all …]
H A DAArch64FastISel.cpp413 Register TmpReg = createResultReg(RC); in materializeFP() local
420 .addReg(TmpReg, getKillRegState(true)); in materializeFP()
4090 Register TmpReg = MRI.createVirtualRegister(RC); in emitLSL_ri() local
4092 TII.get(AArch64::SUBREG_TO_REG), TmpReg) in emitLSL_ri()
4096 Op0 = TmpReg; in emitLSL_ri()
4206 Register TmpReg = MRI.createVirtualRegister(RC); in emitLSR_ri() local
4208 TII.get(AArch64::SUBREG_TO_REG), TmpReg) in emitLSR_ri()
4212 Op0 = TmpReg; in emitLSR_ri()
4311 Register TmpReg = MRI.createVirtualRegister(RC); in emitASR_ri() local
4313 TII.get(AArch64::SUBREG_TO_REG), TmpReg) in emitASR_ri()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp2788 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, 16, IDLoc, STI); in loadImmediate()
2997 TOut.emitRRX(IsPtr64 ? Mips::LD : Mips::LW, TmpReg, TmpReg, in loadAndAddSymbolAddress()
3392 if (!TmpReg) in expandLoadSingleImmToFPR()
3475 if (!TmpReg) in expandLoadDoubleImmToGPR()
3509 if (!TmpReg) in expandLoadDoubleImmToFPR()
3706 if (!TmpReg) in expandMem16Inst()
3783 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, 16, IDLoc, STI); in expandMem16Inst()
3785 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, 16, IDLoc, STI); in expandMem16Inst()
3833 if (!TmpReg) in expandMem9Inst()
4506 if (!TmpReg) in expandUxw()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp153 Register TmpReg = createResultReg(ToRC); in copyRegToRegClass() local
156 return TmpReg; in copyRegToRegClass()
1026 SrcReg = TmpReg; in PPCMoveToFPReg()
1122 SrcReg = TmpReg; in SelectIToFP()
1449 Arg = TmpReg; in processCallArgs()
1461 Arg = TmpReg; in processCallArgs()
1774 SrcReg = TmpReg; in SelectRet()
1783 SrcReg = TmpReg; in SelectRet()
2027 TmpReg) in PPCMaterializeFP()
2047 .addReg(TmpReg) in PPCMaterializeFP()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DThumbRegisterInfo.cpp524 Register TmpReg = MI.getOperand(0).getReg(); in eliminateFrameIndex() local
528 emitThumbRegPlusImmInReg(MBB, II, dl, TmpReg, FrameReg, in eliminateFrameIndex()
531 emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset); in eliminateFrameIndex()
537 BuildMI(MBB, II, dl, TII.get(ARM::tADDhirr), TmpReg) in eliminateFrameIndex()
538 .addReg(TmpReg) in eliminateFrameIndex()
544 emitThumbRegPlusImmediate(MBB, II, dl, TmpReg, FrameReg, Offset, TII, in eliminateFrameIndex()
549 MI.getOperand(FIOperandNum).ChangeToRegister(TmpReg, false, false, true); in eliminateFrameIndex()
H A DMLxExpansionPass.cpp287 Register TmpReg = in ExpandFPMLxInstruction() local
290 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID1, TmpReg) in ExpandFPMLxInstruction()
302 MIB.addReg(TmpReg, getKillRegState(true)) in ExpandFPMLxInstruction()
305 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true)); in ExpandFPMLxInstruction()
H A DThumb1FrameLowering.cpp616 unsigned &TmpReg, MachineRegisterInfo &MRI) { in findTemporariesForLR() argument
617 PopReg = TmpReg = 0; in findTemporariesForLR()
623 TmpReg = 0; in findTemporariesForLR()
628 TmpReg = Reg; in findTemporariesForLR()
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRExpandPseudoInsts.cpp660 TmpReg = scavengeGPR8(MI); in expand()
671 if (TmpReg) in expand()
672 buildMI(MBB, MBBI, AVR::PUSHRr).addReg(TmpReg); in expand()
680 if (TmpReg) { in expand()
780 TmpReg = scavengeGPR8(MI); in expand()
792 if (TmpReg) in expand()
793 buildMI(MBB, MBBI, AVR::PUSHRr).addReg(TmpReg); in expand()
801 if (TmpReg) { in expand()
837 TmpReg = scavengeGPR8(MI); in expandLPMWELPMW()
848 if (TmpReg) in expandLPMWELPMW()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86SpeculativeLoadHardening.cpp1534 Register TmpReg = MRI->createVirtualRegister(PS->RC); in mergePredStateIntoSP() local
1545 .addReg(TmpReg, RegState::Kill); in mergePredStateIntoSP()
1555 Register TmpReg = MRI->createVirtualRegister(PS->RC); in extractPredStateFromSP() local
1560 BuildMI(MBB, InsertPt, Loc, TII->get(TargetOpcode::COPY), TmpReg) in extractPredStateFromSP()
1564 .addReg(TmpReg, RegState::Kill) in extractPredStateFromSP()
1662 Register TmpReg = MRI->createVirtualRegister(OpRC); in hardenLoadAddr() local
1697 TII->get(Is128Bit ? X86::VPORrr : X86::VPORYrr), TmpReg) in hardenLoadAddr()
1728 auto OrI = BuildMI(MBB, InsertPt, Loc, TII->get(OrOp), TmpReg) in hardenLoadAddr()
1751 BuildMI(MBB, InsertPt, Loc, TII->get(X86::SHRX64rr), TmpReg) in hardenLoadAddr()
1764 AddrRegToHardenedReg[Op->getReg()] = TmpReg; in hardenLoadAddr()
[all …]
H A DX86CmovConversion.cpp767 Register TmpReg = MRI->createVirtualRegister(RC); in convertCmovInstsToBranches() local
770 bool Unfolded = TII->unfoldMemoryOperand(*MBB->getParent(), MI, TmpReg, in convertCmovInstsToBranches()
811 FalseBBRegRewriteTable[NewCMOV->getOperand(0).getReg()] = TmpReg; in convertCmovInstsToBranches()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIFixSGPRCopies.cpp283 Register TmpReg = MRI.createVirtualRegister(NewSrcRC); in foldVGPRCopyIntoRegSequence() local
286 TmpReg) in foldVGPRCopyIntoRegSequence()
296 .addReg(TmpReg, RegState::Kill); in foldVGPRCopyIntoRegSequence()
297 TmpReg = TmpAReg; in foldVGPRCopyIntoRegSequence()
300 MI.getOperand(I).setReg(TmpReg); in foldVGPRCopyIntoRegSequence()
647 Register TmpReg in runOnMachineFunction() local
651 TII->get(AMDGPU::V_READFIRSTLANE_B32), TmpReg) in runOnMachineFunction()
653 MI.getOperand(1).setReg(TmpReg); in runOnMachineFunction()
H A DSILowerI1Copies.cpp714 unsigned TmpReg = createLaneMaskReg(*MF); in lowerCopiesToI1() local
715 BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_CMP_NE_U32_e64), TmpReg) in lowerCopiesToI1()
718 MI.getOperand(1).setReg(TmpReg); in lowerCopiesToI1()
719 SrcReg = TmpReg; in lowerCopiesToI1()
H A DSIWholeQuadMode.cpp942 Register TmpReg; in lowerKillI1() local
969 TmpReg = MRI->createVirtualRegister(TRI->getBoolRC()); in lowerKillI1()
971 BuildMI(MBB, MI, DL, TII->get(XorOpc), TmpReg).add(Op).addReg(Exec); in lowerKillI1()
974 .addReg(TmpReg); in lowerKillI1()
1035 if (TmpReg) in lowerKillI1()
1036 LIS->createAndComputeVirtRegInterval(TmpReg); in lowerKillI1()
H A DSIRegisterInfo.cpp2184 Register TmpReg = RS->scavengeRegister(RC, MI, 0, !UseSGPR); in eliminateFrameIndex() local
2185 FIOp.setReg(TmpReg); in eliminateFrameIndex()
2188 if ((!FrameReg || !Offset) && TmpReg) { in eliminateFrameIndex()
2190 auto MIB = BuildMI(*MBB, MI, DL, TII->get(Opc), TmpReg); in eliminateFrameIndex()
2200 UseSGPR ? TmpReg in eliminateFrameIndex()
2206 if ((!TmpSReg && !FrameReg) || (!TmpReg && !UseSGPR)) in eliminateFrameIndex()
2221 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpReg) in eliminateFrameIndex()
2382 Register TmpReg = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0); in eliminateFrameIndex() local
2383 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpReg) in eliminateFrameIndex()
2385 FIOp.ChangeToRegister(TmpReg, false, false, true); in eliminateFrameIndex()
H A DAMDGPUInstructionSelector.cpp1713 Register TmpReg = MRI->createVirtualRegister( in selectImageIntrinsic() local
1717 MIB.addDef(TmpReg); in selectImageIntrinsic()
1720 .addReg(TmpReg, RegState::Kill, SubReg); in selectImageIntrinsic()
2510 BuildMI(*BB, &I, DL, TII.get(Opcode), TmpReg) in selectG_BRCOND()
2513 CondReg = TmpReg; in selectG_BRCOND()
2952 .addReg(TmpReg) in selectG_SHUFFLE_VECTOR()
2954 .addReg(TmpReg); in selectG_SHUFFLE_VECTOR()
2981 .addReg(TmpReg) in selectG_SHUFFLE_VECTOR()
2983 .addReg(TmpReg); in selectG_SHUFFLE_VECTOR()
3003 BuildMI(*MBB, MI, DL, TII.get(AMDGPU::S_LSHR_B32), TmpReg) in selectG_SHUFFLE_VECTOR()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFMISimplifyPatchable.cpp188 Register TmpReg = I->getParent()->getOperand(0).getReg(); in processCandidate() local
189 processDstReg(MRI, TmpReg, DstReg, GVal, false, IsAma); in processCandidate()
/llvm-project-15.0.7/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.cpp353 unsigned TmpReg, SMLoc IDLoc, in emitLoadWithImmOffset() argument
376 emitRI(Mips::LUi, TmpReg, HiOffset, IDLoc, STI); in emitLoadWithImmOffset()
378 emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI); in emitLoadWithImmOffset()
380 emitRRI(Opcode, DstReg, TmpReg, LoOffset, IDLoc, STI); in emitLoadWithImmOffset()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h1290 Register TmpReg; in lookThroughCopyInstrs() local
1291 while (mi_match(Reg, MRI, m_Copy(m_Reg(TmpReg)))) { in lookThroughCopyInstrs()
1292 if (MRI.getType(TmpReg).isValid()) in lookThroughCopyInstrs()
1293 Reg = TmpReg; in lookThroughCopyInstrs()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp763 unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg; in expandCvtFPInt() local
772 TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); in expandCvtFPInt()
777 BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc); in expandCvtFPInt()
778 BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill); in expandCvtFPInt()
H A DMipsTargetStreamer.h163 int64_t Offset, unsigned TmpReg, SMLoc IDLoc,
/llvm-project-15.0.7/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp111 void emitAuipcInstPair(MCOperand DestReg, MCOperand TmpReg,
2339 void RISCVAsmParser::emitAuipcInstPair(MCOperand DestReg, MCOperand TmpReg, in emitAuipcInstPair() argument
2354 Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); in emitAuipcInstPair()
2362 .addOperand(TmpReg) in emitAuipcInstPair()
2447 MCOperand TmpReg = Inst.getOperand(0); in emitLoadStoreSymbol() local
2449 emitAuipcInstPair(DestReg, TmpReg, Symbol, RISCVMCExpr::VK_RISCV_PCREL_HI, in emitLoadStoreSymbol()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTwoAddressInstructionPass.cpp227 Register TmpReg = FromReg; in isRevCopyChain() local
229 MachineInstr *Def = getSingleDef(TmpReg, MBB, MRI); in isRevCopyChain()
233 TmpReg = Def->getOperand(1).getReg(); in isRevCopyChain()
235 if (TmpReg == ToReg) in isRevCopyChain()
/llvm-project-15.0.7/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp427 unsigned BaseReg = 0, IndexReg = 0, TmpReg = 0, Scale = 0; member in __anonad53f99c0111::X86AsmParser::IntelExprStateMachine
676 BaseReg = TmpReg; in onPlus()
680 IndexReg = TmpReg; in onPlus()
735 BaseReg = TmpReg; in onMinus()
739 IndexReg = TmpReg; in onMinus()
790 TmpReg = Reg; in onRegister()
880 IndexReg = TmpReg; in onInteger()
979 BaseReg = TmpReg; in onRBrac()
983 IndexReg = TmpReg; in onRBrac()

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