Lines Matching refs:TmpReg
1713 Register TmpReg = MRI->createVirtualRegister( in selectImageIntrinsic() local
1717 MIB.addDef(TmpReg); in selectImageIntrinsic()
1720 .addReg(TmpReg, RegState::Kill, SubReg); in selectImageIntrinsic()
2509 Register TmpReg = MRI->createVirtualRegister(TRI.getBoolRC()); in selectG_BRCOND() local
2510 BuildMI(*BB, &I, DL, TII.get(Opcode), TmpReg) in selectG_BRCOND()
2513 CondReg = TmpReg; in selectG_BRCOND()
2947 Register TmpReg = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in selectG_SHUFFLE_VECTOR() local
2948 BuildMI(*MBB, MI, DL, TII.get(AMDGPU::V_AND_B32_e32), TmpReg) in selectG_SHUFFLE_VECTOR()
2952 .addReg(TmpReg) in selectG_SHUFFLE_VECTOR()
2954 .addReg(TmpReg); in selectG_SHUFFLE_VECTOR()
2976 Register TmpReg = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in selectG_SHUFFLE_VECTOR() local
2977 BuildMI(*MBB, MI, DL, TII.get(AMDGPU::V_LSHRREV_B32_e64), TmpReg) in selectG_SHUFFLE_VECTOR()
2981 .addReg(TmpReg) in selectG_SHUFFLE_VECTOR()
2983 .addReg(TmpReg); in selectG_SHUFFLE_VECTOR()
3002 Register TmpReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectG_SHUFFLE_VECTOR() local
3003 BuildMI(*MBB, MI, DL, TII.get(AMDGPU::S_LSHR_B32), TmpReg) in selectG_SHUFFLE_VECTOR()
3007 .addReg(TmpReg) in selectG_SHUFFLE_VECTOR()