Lines Matching refs:TmpReg
307 Register TmpReg = VE::SX16; in processSTVM() local
309 build(VE::SVMmr, TmpReg).addReg(SrcReg).addImm(i); in processSTVM()
312 TmpReg, getKillRegState(true)); in processSTVM()
316 build(VE::SVMmr, TmpReg).addReg(SrcReg, getKillRegState(isKill)).addImm(3); in processSTVM()
318 MI.getOperand(3).ChangeToRegister(TmpReg, false, false, true); in processSTVM()
344 unsigned TmpReg = VE::SX16; in processLDVM() local
348 build(VE::LDrii, TmpReg).addReg(FrameReg).addImm(0).addImm(0); in processLDVM()
354 MI.getOperand(0).ChangeToRegister(TmpReg, true); in processLDVM()
359 build(VE::LVMir, DestReg).addImm(i).addReg(TmpReg, getKillRegState(true)); in processLDVM()
363 .addReg(TmpReg, getKillRegState(true)) in processLDVM()
368 .addReg(TmpReg, getKillRegState(true)) in processLDVM()
387 Register TmpReg = VE::SX16; in processSTVM512() local
391 LastMI = build(VE::SVMmr, TmpReg).addReg(SrcLoReg).addImm(i); in processSTVM512()
394 TmpReg, getKillRegState(true)); in processSTVM512()
402 build(VE::SVMmr, TmpReg).addReg(SrcHiReg).addImm(i); in processSTVM512()
405 TmpReg, getKillRegState(true)); in processSTVM512()
409 LastMI = build(VE::SVMmr, TmpReg).addReg(SrcHiReg).addImm(3); in processSTVM512()
416 MI.getOperand(3).ChangeToRegister(TmpReg, false, false, true); in processSTVM512()
432 Register TmpReg = VE::SX16; in processLDVM512() local
436 build(VE::LDrii, TmpReg).addReg(FrameReg).addImm(0).addImm(0); in processLDVM512()
440 .addReg(TmpReg, getKillRegState(true)) in processLDVM512()
446 build(VE::LDrii, TmpReg).addReg(FrameReg).addImm(0).addImm(0); in processLDVM512()
450 .addReg(TmpReg, getKillRegState(true)) in processLDVM512()
455 MI.getOperand(0).ChangeToRegister(TmpReg, true); in processLDVM512()
458 .addReg(TmpReg, getKillRegState(true)) in processLDVM512()