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Searched refs:SubRegIdx (Results 1 – 25 of 30) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVExpandPseudoInsts.cpp300 unsigned SubRegIdx = RISCV::sub_vrm1_0; in expandVSPILL() local
305 SubRegIdx = RISCV::sub_vrm2_0; in expandVSPILL()
310 SubRegIdx = RISCV::sub_vrm4_0; in expandVSPILL()
322 .addReg(TRI->getSubReg(SrcReg, SubRegIdx + I)) in expandVSPILL()
350 unsigned SubRegIdx = RISCV::sub_vrm1_0; in expandVRELOAD() local
355 SubRegIdx = RISCV::sub_vrm2_0; in expandVRELOAD()
360 SubRegIdx = RISCV::sub_vrm4_0; in expandVRELOAD()
368 TRI->getSubReg(DestReg, SubRegIdx + I)) in expandVRELOAD()
H A DRISCVInstrInfo.cpp306 SubRegIdx = RISCV::sub_vrm1_0; in copyPhysReg()
311 SubRegIdx = RISCV::sub_vrm2_0; in copyPhysReg()
316 SubRegIdx = RISCV::sub_vrm4_0; in copyPhysReg()
321 SubRegIdx = RISCV::sub_vrm1_0; in copyPhysReg()
326 SubRegIdx = RISCV::sub_vrm2_0; in copyPhysReg()
331 SubRegIdx = RISCV::sub_vrm1_0; in copyPhysReg()
336 SubRegIdx = RISCV::sub_vrm2_0; in copyPhysReg()
341 SubRegIdx = RISCV::sub_vrm1_0; in copyPhysReg()
346 SubRegIdx = RISCV::sub_vrm1_0; in copyPhysReg()
351 SubRegIdx = RISCV::sub_vrm1_0; in copyPhysReg()
[all …]
H A DRISCVISelDAGToDAG.cpp330 unsigned SubRegIdx = RISCVTargetLowering::getSubregIndexByMVT(VT, I); in selectVLSEG() local
332 CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, SuperReg)); in selectVLSEG()
374 unsigned SubRegIdx = RISCVTargetLowering::getSubregIndexByMVT(VT, I); in selectVLSEGFF() local
376 CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, SuperReg)); in selectVLSEGFF()
429 unsigned SubRegIdx = RISCVTargetLowering::getSubregIndexByMVT(VT, I); in selectVLXSEG() local
1591 unsigned SubRegIdx; in Select() local
1592 std::tie(SubRegIdx, Idx) = in Select()
1613 if (SubRegIdx == RISCV::NoSubRegister) { in Select()
1644 unsigned SubRegIdx; in Select() local
1645 std::tie(SubRegIdx, Idx) = in Select()
[all …]
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DRenameIndependentSubregs.cpp182 unsigned SubRegIdx = MO.getSubReg(); in findComponents() local
183 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx); in findComponents()
226 unsigned SubRegIdx = MO.getSubReg(); in rewriteOperands() local
227 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx); in rewriteOperands()
348 unsigned SubRegIdx = MO.getSubReg(); in computeMainRangesFixFlags() local
349 if (SubRegIdx == 0) in computeMainRangesFixFlags()
H A DRegisterPressure.cpp535 unsigned SubRegIdx = MO.getSubReg(); in collectOperandLanes() local
538 pushRegLanes(Reg, SubRegIdx, RegOpers.Uses); in collectOperandLanes()
543 SubRegIdx = 0; in collectOperandLanes()
547 pushRegLanes(Reg, SubRegIdx, RegOpers.DeadDefs); in collectOperandLanes()
549 pushRegLanes(Reg, SubRegIdx, RegOpers.Defs); in collectOperandLanes()
553 void pushRegLanes(Register Reg, unsigned SubRegIdx, in pushRegLanes() argument
556 LaneBitmask LaneMask = SubRegIdx != 0 in pushRegLanes()
557 ? TRI.getSubRegIndexLaneMask(SubRegIdx) in pushRegLanes()
1235 unsigned SubRegIdx = MO.getSubReg(); in findUseBetween() local
1236 LaneBitmask UseMask = TRI.getSubRegIndexLaneMask(SubRegIdx); in findUseBetween()
H A DVirtRegMap.cpp396 unsigned SubRegIdx = MO.getSubReg(); in readsUndefSubreg() local
397 assert(SubRegIdx != 0 && LI.hasSubRanges()); in readsUndefSubreg()
398 LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(SubRegIdx); in readsUndefSubreg()
H A DStackMaps.cpp251 unsigned SubRegIdx = TRI->getSubRegIndex(LLVMRegNum, MOI->getReg()); in parseOperand() local
252 if (SubRegIdx) in parseOperand()
253 Offset = TRI->getSubRegIdxOffset(SubRegIdx); in parseOperand()
H A DRegAllocFast.cpp857 unsigned SubRegIdx = MO.getSubReg(); in allocVirtRegUndef() local
858 if (SubRegIdx != 0) { in allocVirtRegUndef()
859 PhysReg = TRI->getSubReg(PhysReg, SubRegIdx); in allocVirtRegUndef()
H A DMachineVerifier.cpp2301 const unsigned SubRegIdx = MO->getSubReg(); in checkLiveness() local
2307 if (SubRegIdx != 0 && (MO->isDef() || !MO->isUndef()) && !LI->empty() && in checkLiveness()
2349 LaneBitmask MOMask = SubRegIdx != 0 in checkLiveness()
2350 ? TRI->getSubRegIndexLaneMask(SubRegIdx) in checkLiveness()
2441 LaneBitmask MOMask = SubRegIdx != 0 in checkLiveness()
2442 ? TRI->getSubRegIndexLaneMask(SubRegIdx) in checkLiveness()
H A DRegisterCoalescer.cpp329 MachineOperand &MO, unsigned SubRegIdx);
1720 MachineOperand &MO, unsigned SubRegIdx) { in addUndefFlag() argument
1721 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubRegIdx); in addUndefFlag()
1874 unsigned SubRegIdx = MO.getSubReg(); in setUndefOnPrunedSubRegUses() local
1875 if (SubRegIdx == 0 || MO.isUndef()) in setUndefOnPrunedSubRegUses()
1878 LaneBitmask SubRegMask = TRI->getSubRegIndexLaneMask(SubRegIdx); in setUndefOnPrunedSubRegUses()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSILoadStoreOptimizer.cpp1321 const unsigned SubRegIdx0 = std::get<0>(SubRegIdx); in mergeSBufferLoadImmPair()
1322 const unsigned SubRegIdx1 = std::get<1>(SubRegIdx); in mergeSBufferLoadImmPair()
1377 const unsigned SubRegIdx0 = std::get<0>(SubRegIdx); in mergeBufferLoadPair()
1378 const unsigned SubRegIdx1 = std::get<1>(SubRegIdx); in mergeBufferLoadPair()
1437 const unsigned SubRegIdx0 = std::get<0>(SubRegIdx); in mergeTBufferLoadPair()
1438 const unsigned SubRegIdx1 = std::get<1>(SubRegIdx); in mergeTBufferLoadPair()
1466 const unsigned SubRegIdx0 = std::get<0>(SubRegIdx); in mergeTBufferStorePair()
1467 const unsigned SubRegIdx1 = std::get<1>(SubRegIdx); in mergeTBufferStorePair()
1536 const unsigned SubRegIdx0 = std::get<0>(SubRegIdx); in mergeFlatLoadPair()
1537 const unsigned SubRegIdx1 = std::get<1>(SubRegIdx); in mergeFlatLoadPair()
[all …]
H A DAMDGPUInstructionSelector.cpp2017 int SubRegIdx = sizeToSubRegIndex(DstSize); in selectG_TRUNC() local
2018 if (SubRegIdx == -1) in selectG_TRUNC()
2024 = TRI.getSubClassWithSubReg(SrcRC, SubRegIdx); in selectG_TRUNC()
2033 I.getOperand(1).setSubReg(SubRegIdx); in selectG_TRUNC()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86FixupBWInsts.cpp197 const auto SubRegIdx = TRI->getSubRegIndex(SuperDestReg, OrigDestReg); in getSuperRegDestIfDead() local
203 if (SubRegIdx == X86::sub_8bit_hi) in getSuperRegDestIfDead()
211 if (SubRegIdx != X86::sub_8bit) in getSuperRegDestIfDead()
H A DX86ISelDAGToDAG.cpp1571 unsigned SubRegIdx = N->getConstantOperandVal(2); in PostprocessISelDAG() local
1572 if (SubRegIdx != X86::sub_xmm && SubRegIdx != X86::sub_ymm) in PostprocessISelDAG()
5623 unsigned SubRegIdx; in Select() local
5639 SubRegIdx = 0; in Select()
5647 SubRegIdx = 0; in Select()
5656 SubRegIdx = X86::sub_8bit; in Select()
5662 SubRegIdx = X86::sub_16bit; in Select()
5668 SubRegIdx = X86::sub_32bit; in Select()
5679 if (SubRegIdx != 0) { in Select()
5681 CurDAG->getTargetExtractSubreg(SubRegIdx, dl, SubRegVT, Shift); in Select()
H A DX86InstrAVX512.td93 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
3195 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)),
3196 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src2, Narrow.SubRegIdx)),
3219 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)),
3729 Narrow.SubRegIdx)>;
3738 Narrow.SubRegIdx)>;
10573 _.RC:$src, _.SubRegIdx)),
11406 _.info256.SubRegIdx)),
11407 _.info256.SubRegIdx)>;
11414 _.info128.SubRegIdx)),
[all …]
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEInstrInfo.cpp330 const unsigned *SubRegIdx, in copyPhysSubRegs() argument
335 Register SubDest = TRI->getSubReg(DestReg, SubRegIdx[Idx]); in copyPhysSubRegs()
336 Register SubSrc = TRI->getSubReg(SrcReg, SubRegIdx[Idx]); in copyPhysSubRegs()
393 const unsigned SubRegIdx[] = {VE::sub_vm_even, VE::sub_vm_odd}; in copyPhysReg() local
396 NumSubRegs, SubRegIdx, &getRegisterInfo()); in copyPhysReg()
399 const unsigned SubRegIdx[] = {VE::sub_even, VE::sub_odd}; in copyPhysReg() local
402 NumSubRegs, SubRegIdx, &getRegisterInfo()); in copyPhysReg()
/llvm-project-15.0.7/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp475 CodeGenSubRegIndex *SubRegIdx; in computeSecondarySubRegs() local
477 std::tie(SubRegIdx, SubReg) = SubRegQueue.front(); in computeSecondarySubRegs()
495 assert(getSubRegIndex(SubReg) == SubRegIdx && "LeadingSuperRegs correct"); in computeSecondarySubRegs()
497 if (CodeGenSubRegIndex *SubRegIdx = getSubRegIndex(SubReg)) { in computeSecondarySubRegs() local
498 if (SubRegIdx->ConcatenationOf.empty()) in computeSecondarySubRegs()
499 Parts.push_back(SubRegIdx); in computeSecondarySubRegs()
501 append_range(Parts, SubRegIdx->ConcatenationOf); in computeSecondarySubRegs()
H A DGlobalISelEmitter.cpp2850 const CodeGenSubRegIndex *SubRegIdx; member in __anoncee47b830111::TempRegRenderer
2859 SubRegIdx(SubReg), IsDef(IsDef), IsDead(IsDead) {} in TempRegRenderer()
2866 if (SubRegIdx) { in emitRenderOpcodes()
2885 if (SubRegIdx) in emitRenderOpcodes()
2886 Table << MatchTable::NamedValue(SubRegIdx->getQualifiedName()); in emitRenderOpcodes()
2916 const CodeGenSubRegIndex *SubRegIdx; member in __anoncee47b830111::SubRegIndexRenderer
2920 : OperandRenderer(OR_SubRegIndex), InsnID(InsnID), SubRegIdx(SRI) {} in SubRegIndexRenderer()
2929 << MatchTable::IntValue(SubRegIdx->EnumValue) in emitRenderOpcodes()
/llvm-project-15.0.7/llvm/test/TableGen/
H A DGlobalISelEmitterSubreg.td136 // CHECK-NEXT: GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/1, // src
193 // CHECK-NEXT: GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/1, // src
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/
H A DInstructionSelectorImpl.h910 int64_t SubRegIdx = MatchTable[CurrentIdx++]; in executeMatchTable() local
913 0, SubRegIdx); in executeMatchTable()
917 << OpIdx << ", " << SubRegIdx << ")\n"); in executeMatchTable()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp1974 SDValue SubRegIdx = CurDAG->getTargetConstant(PPC::sub_32, dl, MVT::i32); in ExtendToInt64() local
1979 SubRegIdx), 0); in ExtendToInt64()
1988 SDValue SubRegIdx = CurDAG->getTargetConstant(PPC::sub_32, dl, MVT::i32); in TruncateToInt32() local
3062 SDValue SubRegIdx = in addExtOrTrunc() local
3065 ImDef, NatWidthRes, SubRegIdx), 0); in addExtOrTrunc()
3072 SDValue SubRegIdx = in addExtOrTrunc() local
3075 NatWidthRes, SubRegIdx), 0); in addExtOrTrunc()
5111 SDValue SubRegIdx = CurDAG->getTargetConstant(SubReg, dl, MVT::i32); in Select() local
5114 CR6Reg, SubRegIdx, BCDOp.getValue(1)), in Select()
5164 SDValue SubRegIdx = CurDAG->getTargetConstant(PPC::sub_eq, dl, MVT::i32); in Select() local
[all …]
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelDAGToDAG.cpp1170 unsigned SubRegIdx = in loadVectorConstant() local
1173 Node, CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, Op).getNode()); in loadVectorConstant()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp324 unsigned SubRegIdx);
326 unsigned SubRegIdx);
1483 unsigned SubRegIdx) { in SelectLoad() argument
1497 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectLoad()
1512 unsigned Opc, unsigned SubRegIdx) { in SelectPostLoad() argument
1536 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectPostLoad()
/llvm-project-15.0.7/llvm/lib/CodeGen/LiveDebugValues/
H A DInstrRefBasedImpl.cpp1525 unsigned SubRegIdx = SRI.getSubRegIndex(); in performCopy() local
1526 unsigned DstSubReg = TRI->getSubReg(DstRegNum, SubRegIdx); in performCopy()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp3331 unsigned SubRegIdx = Subtarget.isABI_N64() ? Mips::sub_32 : 0; in emitINSERT_DF_VIDX() local
3388 .addReg(LaneReg, 0, SubRegIdx); in emitINSERT_DF_VIDX()
3417 .addReg(LaneTmp2, 0, SubRegIdx); in emitINSERT_DF_VIDX()

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