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Searched refs:ShiftC (Results 1 – 9 of 9) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/
H A DInstCombineAndOrXor.cpp1810 const APInt *ShiftC; in visitAnd() local
1811 if (match(Op0, m_OneUse(m_SExt(m_AShr(m_Value(X), m_APInt(ShiftC))))) && in visitAnd()
1812 ShiftC->ult(Width)) { in visitAnd()
1813 if (*C == APInt::getLowBitsSet(Width, Width - ShiftC->getZExtValue())) { in visitAnd()
1817 Constant *ShAmtC = ConstantInt::get(Ty, ShiftC->zext(Width)); in visitAnd()
1824 if (match(Op0, m_AShr(m_Value(X), m_APInt(ShiftC))) && ShiftC->ult(Width) && in visitAnd()
1825 C->isMask(Width - ShiftC->getZExtValue())) in visitAnd()
1826 return BinaryOperator::CreateLShr(X, ConstantInt::get(Ty, *ShiftC)); in visitAnd()
1933 match(Op0, m_OneUse(m_LogicalShift(m_Power2(ShiftC), m_Value(X))))) { in visitAnd()
1934 int Log2ShiftC = ShiftC->exactLogBase2(); in visitAnd()
H A DInstCombineSimplifyDemanded.cpp536 Constant *ShiftC = ConstantInt::get(VTy, CTZ); in SimplifyDemandedUseBits() local
537 Instruction *Shl = BinaryOperator::CreateShl(I->getOperand(0), ShiftC); in SimplifyDemandedUseBits()
/llvm-project-15.0.7/llvm/lib/Transforms/Utils/
H A DSimplifyCFG.cpp6554 auto *ShiftC = ConstantInt::get(Ty, Shift); in ReduceSwitchRange() local
6556 auto *LShr = Builder.CreateLShr(Sub, ShiftC); in ReduceSwitchRange()
6565 cast<ConstantInt>(ConstantInt::get(Ty, Sub.lshr(ShiftC->getValue())))); in ReduceSwitchRange()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp5674 SDValue ShiftC = CurDAG->getTargetConstant(ShiftAmt, dl, MVT::i64); in Select() local
5677 N0.getOperand(0), ShiftC), in Select()
H A DX86ISelLowering.cpp46699 auto *ShiftC = dyn_cast<ConstantSDNode>(N1); in combineShiftRightLogical() local
46701 if (!ShiftC || !AndC) in combineShiftRightLogical()
46716 APInt NewMaskVal = MaskVal.lshr(ShiftC->getAPIntValue()); in combineShiftRightLogical()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp1568 if (ConstantSDNode *ShiftC = in SimplifyDemandedBits() local
1572 if (ShiftC->getAPIntValue().ult(BitWidth)) { in SimplifyDemandedBits()
1573 uint64_t ShiftAmt = ShiftC->getZExtValue(); in SimplifyDemandedBits()
H A DDAGCombiner.cpp9371 SDValue ShiftC = in visitSRA() local
9377 Add = DAG.getNode(ISD::ADD, DL, TruncVT, Trunc, ShiftC); in visitSRA()
9379 Add = DAG.getNode(ISD::SUB, DL, TruncVT, ShiftC, Trunc); in visitSRA()
12964 SDValue ShiftC = DAG.getConstant(ShAmt, DL, VT); in reduceLoadWidth() local
12965 Result = DAG.getNode(ISD::SHL, DL, VT, Result, ShiftC); in reduceLoadWidth()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp13682 auto *ShiftC = dyn_cast<ConstantSDNode>(N->getOperand(0).getOperand(1)); in isDesirableToCommuteXorWithShift() local
13683 if (XorC && ShiftC) { in isDesirableToCommuteXorWithShift()
13686 unsigned ShiftAmt = ShiftC->getZExtValue(); in isDesirableToCommuteXorWithShift()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp13622 auto *ShiftC = dyn_cast<ConstantSDNode>(N->getOperand(0).getOperand(1)); in isDesirableToCommuteXorWithShift() local
13623 if (XorC && ShiftC) { in isDesirableToCommuteXorWithShift()
13626 unsigned ShiftAmt = ShiftC->getZExtValue(); in isDesirableToCommuteXorWithShift()