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Searched refs:ShiftAmt (Results 1 – 25 of 57) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Support/
H A DKnownBits.cpp203 ShiftAmt <= MaxShiftAmt; ++ShiftAmt) { in shl()
205 if ((ShiftAmtZeroMask & ShiftAmt) != ShiftAmt || in shl()
206 (ShiftAmtOneMask | ShiftAmt) != ShiftAmt) in shl()
210 SpecificShift.One = LHS.One << ShiftAmt; in shl()
256 ShiftAmt <= MaxShiftAmt; ++ShiftAmt) { in lshr()
258 if ((ShiftAmtZeroMask & ShiftAmt) != ShiftAmt || in lshr()
259 (ShiftAmtOneMask | ShiftAmt) != ShiftAmt) in lshr()
263 SpecificShift.One.lshrInPlace(ShiftAmt); in lshr()
314 ShiftAmt <= MaxShiftAmt; ++ShiftAmt) { in ashr()
316 if ((ShiftAmtZeroMask & ShiftAmt) != ShiftAmt || in ashr()
[all …]
H A DAPInt.cpp1018 void APInt::ashrSlowCase(unsigned ShiftAmt) { in ashrSlowCase() argument
1020 if (!ShiftAmt) in ashrSlowCase()
1027 unsigned WordShift = ShiftAmt / APINT_BITS_PER_WORD; in ashrSlowCase()
1028 unsigned BitShift = ShiftAmt % APINT_BITS_PER_WORD; in ashrSlowCase()
1067 void APInt::lshrSlowCase(unsigned ShiftAmt) { in lshrSlowCase() argument
1068 tcShiftRight(U.pVal, getNumWords(), ShiftAmt); in lshrSlowCase()
1079 void APInt::shlSlowCase(unsigned ShiftAmt) { in shlSlowCase() argument
1080 tcShiftLeft(U.pVal, getNumWords(), ShiftAmt); in shlSlowCase()
2231 unsigned ShiftAmt = (Radix == 16 ? 4 : (Radix == 8 ? 3 : 1)); in toString() local
2237 Tmp.lshrInPlace(ShiftAmt); in toString()
/llvm-project-15.0.7/llvm/test/Transforms/AtomicExpand/SPARC/
H A Dpartword.ll19 ; CHECK: %ShiftAmt = trunc i64 %3 to i32
20 ; CHECK: %Mask = shl i32 255, %ShiftAmt
23 ; CHECK: %5 = shl i32 %4, %ShiftAmt
25 ; CHECK: %7 = shl i32 %6, %ShiftAmt
42 ; CHECK: %shifted = lshr i32 %14, %ShiftAmt
64 ; CHECK: %ShiftAmt = trunc i64 %3 to i32
65 ; CHECK: %Mask = shl i32 65535, %ShiftAmt
68 ; CHECK: %5 = shl i32 %4, %ShiftAmt
70 ; CHECK: %7 = shl i32 %6, %ShiftAmt
110 ; CHECK: %ShiftAmt = trunc i64 %3 to i32
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ExpandImm.cpp69 unsigned ShiftAmt = 0; in tryToreplicateChunks() local
72 for (; ShiftAmt < 64; ShiftAmt += 16) { in tryToreplicateChunks()
73 Imm16 = (UImm >> ShiftAmt) & 0xFFFF; in tryToreplicateChunks()
81 AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt) }); in tryToreplicateChunks()
89 for (ShiftAmt += 16; ShiftAmt < 64; ShiftAmt += 16) { in tryToreplicateChunks()
90 Imm16 = (UImm >> ShiftAmt) & 0xFFFF; in tryToreplicateChunks()
96 AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt) }); in tryToreplicateChunks()
H A DAArch64ConditionOptimizer.cpp175 unsigned ShiftAmt = AArch64_AM::getShiftValue(I.getOperand(3).getImm()); in findSuitableCompare() local
179 } else if (I.getOperand(2).getImm() << ShiftAmt >= 0xfff) { in findSuitableCompare()
H A DAArch64ISelDAGToDAG.cpp487 unsigned ShiftAmt; in SelectArithImmed() local
490 ShiftAmt = 0; in SelectArithImmed()
492 ShiftAmt = 12; in SelectArithImmed()
2327 Mask <<= ShiftAmt; in getUsefulBitsFromOrWithShiftedReg()
2329 Mask.lshrInPlace(ShiftAmt); in getUsefulBitsFromOrWithShiftedReg()
2335 Mask.lshrInPlace(ShiftAmt); in getUsefulBitsFromOrWithShiftedReg()
2337 Mask <<= ShiftAmt; in getUsefulBitsFromOrWithShiftedReg()
2903 SDValue ShiftAmt = N->getOperand(1); in tryShiftAmountMod() local
2910 ShiftAmt = ShiftAmt->getOperand(0); in tryShiftAmountMod()
2912 if (ShiftAmt->getOpcode() == ISD::ADD || ShiftAmt->getOpcode() == ISD::SUB) { in tryShiftAmountMod()
[all …]
/llvm-project-15.0.7/llvm/lib/Analysis/
H A DDemandedBits.cpp156 uint64_t ShiftAmt = SA->urem(BitWidth); in determineLiveOperandBits() local
158 ShiftAmt = BitWidth - ShiftAmt; in determineLiveOperandBits()
161 AB = AOut.lshr(ShiftAmt); in determineLiveOperandBits()
163 AB = AOut.shl(BitWidth - ShiftAmt); in determineLiveOperandBits()
205 AB = AOut.lshr(ShiftAmt); in determineLiveOperandBits()
211 AB |= APInt::getHighBitsSet(BitWidth, ShiftAmt+1); in determineLiveOperandBits()
213 AB |= APInt::getHighBitsSet(BitWidth, ShiftAmt); in determineLiveOperandBits()
222 AB = AOut.shl(ShiftAmt); in determineLiveOperandBits()
227 AB |= APInt::getLowBitsSet(BitWidth, ShiftAmt); in determineLiveOperandBits()
236 AB = AOut.shl(ShiftAmt); in determineLiveOperandBits()
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H A DValueTracking.cpp1063 for (unsigned ShiftAmt = 0; ShiftAmt < BitWidth; ++ShiftAmt) { in computeKnownBitsFromShiftOperator() local
1066 if ((ShiftAmt & ~ShiftAmtKZ) != ShiftAmt) in computeKnownBitsFromShiftOperator()
1068 if ((ShiftAmt | ShiftAmtKO) != ShiftAmt) in computeKnownBitsFromShiftOperator()
1073 if (ShiftAmt == 0) { in computeKnownBitsFromShiftOperator()
1082 Known, KF(Known2, KnownBits::makeConstant(APInt(32, ShiftAmt)))); in computeKnownBitsFromShiftOperator()
1662 uint64_t ShiftAmt = SA->urem(BitWidth); in computeKnownBitsFromOperator() local
1664 ShiftAmt = BitWidth - ShiftAmt; in computeKnownBitsFromOperator()
1671 Known2.Zero.shl(ShiftAmt) | Known3.Zero.lshr(BitWidth - ShiftAmt); in computeKnownBitsFromOperator()
1673 Known2.One.shl(ShiftAmt) | Known3.One.lshr(BitWidth - ShiftAmt); in computeKnownBitsFromOperator()
H A DConstantFolding.cpp218 unsigned ShiftAmt = isLittleEndian ? 0 : SrcBitSize*(Ratio-1); in FoldBitCast() local
234 ConstantInt::get(Src->getType(), ShiftAmt)); in FoldBitCast()
235 ShiftAmt += isLittleEndian ? SrcBitSize : -SrcBitSize; in FoldBitCast()
266 unsigned ShiftAmt = isLittleEndian ? 0 : DstBitSize*(Ratio-1); in FoldBitCast() local
271 ConstantInt::get(Src->getType(), ShiftAmt)); in FoldBitCast()
272 ShiftAmt += isLittleEndian ? DstBitSize : -DstBitSize; in FoldBitCast()
/llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/
H A DInstCombineSimplifyDemanded.cpp598 Known.Zero <<= ShiftAmt; in SimplifyDemandedUseBits()
599 Known.One <<= ShiftAmt; in SimplifyDemandedUseBits()
601 if (ShiftAmt) in SimplifyDemandedUseBits()
602 Known.Zero.setLowBits(ShiftAmt); in SimplifyDemandedUseBits()
669 DemandedMaskIn.setLowBits(ShiftAmt); in SimplifyDemandedUseBits()
674 Known.Zero.lshrInPlace(ShiftAmt); in SimplifyDemandedUseBits()
675 Known.One.lshrInPlace(ShiftAmt); in SimplifyDemandedUseBits()
676 if (ShiftAmt) in SimplifyDemandedUseBits()
726 Known.Zero.lshrInPlace(ShiftAmt); in SimplifyDemandedUseBits()
727 Known.One.lshrInPlace(ShiftAmt); in SimplifyDemandedUseBits()
[all …]
H A DInstCombineCasts.cpp1187 uint64_t ShiftAmt = Amt->getZExtValue(); in canEvaluateZExtd() local
1188 BitsToClear = ShiftAmt < BitsToClear ? BitsToClear - ShiftAmt : 0; in canEvaluateZExtd()
1409 unsigned ShiftAmt = KnownZeroMask.countTrailingZeros(); in transformSExtICmp() local
1411 if (ShiftAmt) in transformSExtICmp()
1413 ConstantInt::get(In->getType(), ShiftAmt)); in transformSExtICmp()
1423 unsigned ShiftAmt = KnownZeroMask.countLeadingZeros(); in transformSExtICmp() local
1425 if (ShiftAmt) in transformSExtICmp()
1427 ConstantInt::get(In->getType(), ShiftAmt)); in transformSExtICmp()
H A DInstCombineCompares.cpp2127 const APInt *ShiftAmt; in foldICmpShlConstant() local
2128 if (!match(Shl->getOperand(1), m_APInt(ShiftAmt))) in foldICmpShlConstant()
2134 if (ShiftAmt->uge(TypeBits)) in foldICmpShlConstant()
2147 APInt ShiftedC = C.ashr(*ShiftAmt); in foldICmpShlConstant()
2151 C.ashr(*ShiftAmt).shl(*ShiftAmt) == C) { in foldICmpShlConstant()
2152 APInt ShiftedC = C.ashr(*ShiftAmt); in foldICmpShlConstant()
2161 APInt ShiftedC = (C - 1).ashr(*ShiftAmt) + 1; in foldICmpShlConstant()
2177 APInt ShiftedC = C.lshr(*ShiftAmt); in foldICmpShlConstant()
2181 C.lshr(*ShiftAmt).shl(*ShiftAmt) == C) { in foldICmpShlConstant()
2182 APInt ShiftedC = C.lshr(*ShiftAmt); in foldICmpShlConstant()
[all …]
/llvm-project-15.0.7/llvm/include/llvm/ADT/
H A DAPInt.h769 if (ShiftAmt == BitWidth)
772 U.VAL <<= ShiftAmt;
775 shlSlowCase(ShiftAmt);
810 R.ashrInPlace(ShiftAmt); in ashr()
819 if (ShiftAmt == BitWidth) in ashrInPlace()
826 ashrSlowCase(ShiftAmt); in ashrInPlace()
845 U.VAL >>= ShiftAmt; in lshrInPlace()
848 lshrSlowCase(ShiftAmt); in lshrInPlace()
871 R.ashrInPlace(ShiftAmt); in ashr()
883 R.lshrInPlace(ShiftAmt); in lshr()
[all …]
/llvm-project-15.0.7/llvm/lib/Transforms/Utils/
H A DVNCoercion.cpp137 uint64_t ShiftAmt = DL.getTypeStoreSizeInBits(StoredValTy).getFixedSize() - in coerceAvailableValueToLoadType() local
140 StoredVal, ConstantInt::get(StoredVal->getType(), ShiftAmt)); in coerceAvailableValueToLoadType()
423 unsigned ShiftAmt; in getStoreValueForLoadHelper() local
425 ShiftAmt = Offset * 8; in getStoreValueForLoadHelper()
427 ShiftAmt = (StoreSize - LoadSize - Offset) * 8; in getStoreValueForLoadHelper()
428 if (ShiftAmt) in getStoreValueForLoadHelper()
430 ConstantInt::get(SrcVal->getType(), ShiftAmt)); in getStoreValueForLoadHelper()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerCombiner.cpp173 unsigned ShiftAmt, AddSubOpc; in matchAArch64MulConstCombine() local
186 ShiftAmt = SCVMinus1.logBase2(); in matchAArch64MulConstCombine()
189 ShiftAmt = CVPlus1.logBase2(); in matchAArch64MulConstCombine()
199 ShiftAmt = CVNegPlus1.logBase2(); in matchAArch64MulConstCombine()
203 ShiftAmt = CVNegMinus1.logBase2(); in matchAArch64MulConstCombine()
214 auto Shift = B.buildConstant(LLT::scalar(64), ShiftAmt); in matchAArch64MulConstCombine()
H A DAArch64PostLegalizerLowering.cpp780 uint64_t ShiftAmt = MaybeShiftAmt->Value.getZExtValue(); in getCmpOperandFoldingProfit() local
788 return (ShiftAmt <= 4) ? 2 : 1; in getCmpOperandFoldingProfit()
794 if ((ShiftSize == 32 && ShiftAmt <= 31) || in getCmpOperandFoldingProfit()
795 (ShiftSize == 64 && ShiftAmt <= 63)) in getCmpOperandFoldingProfit()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUPostLegalizerCombiner.cpp260 int64_t ShiftAmt; in matchCvtF32UByteN() local
261 bool IsShr = mi_match(SrcReg, MRI, m_GLShr(m_Reg(Src0), m_ICst(ShiftAmt))); in matchCvtF32UByteN()
262 if (IsShr || mi_match(SrcReg, MRI, m_GShl(m_Reg(Src0), m_ICst(ShiftAmt)))) { in matchCvtF32UByteN()
267 ShiftOffset += ShiftAmt; in matchCvtF32UByteN()
269 ShiftOffset -= ShiftAmt; in matchCvtF32UByteN()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DAtomicExpandPass.cpp632 Value *ShiftAmt = nullptr; member
655 PrintObj(PMV.ShiftAmt); in operator <<()
699 PMV.ShiftAmt = ConstantInt::get(PMV.ValueType, 0); in createMaskInstrs()
719 PMV.ShiftAmt = Builder.CreateShl(PtrLSB, 3); in createMaskInstrs()
722 PMV.ShiftAmt = Builder.CreateShl( in createMaskInstrs()
726 PMV.ShiftAmt = Builder.CreateTrunc(PMV.ShiftAmt, PMV.WordType, "ShiftAmt"); in createMaskInstrs()
740 Value *Shift = Builder.CreateLShr(WideWord, PMV.ShiftAmt, "shifted"); in extractMaskedValue()
754 Builder.CreateShl(ZExt, PMV.ShiftAmt, "shifted", /*HasNUW*/ true); in insertMaskedValue()
827 PMV.ShiftAmt, "ValOperand_Shifted"); in expandPartwordAtomicRMW()
866 PMV.ShiftAmt, "ValOperand_Shifted"); in widenPartwordAtomicRMW()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp1983 if (ShiftAmt != 1 && ShiftAmt != 2 && ShiftAmt != 3) in foldMaskedShiftToScaledMask()
2009 AM.Scale = 1 << ShiftAmt; in foldMaskedShiftToScaledMask()
3576 NBits = ShiftAmt; in matchBitExtract()
3752 SDValue OrigShiftAmt = ShiftAmt; in matchBitExtract()
3753 ShiftAmt = CurDAG->getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShiftAmt); in matchBitExtract()
3978 SDValue ShiftAmt = OrigShiftAmt; in tryShiftAmountMod() local
3983 ShiftAmt = ShiftAmt->getOperand(0); in tryShiftAmountMod()
3989 if (ShiftAmt->getOpcode() == ISD::ADD || ShiftAmt->getOpcode() == ISD::SUB) { in tryShiftAmountMod()
5622 unsigned ShiftAmt; in Select() local
5638 ShiftAmt = TrailingZeros; in Select()
[all …]
H A DX86InstCombineIntrinsic.cpp286 auto ShiftAmt = ConstantInt::get(SVT, Count.zextOrTrunc(BitWidth)); in simplifyX86immShift() local
287 auto ShiftVec = Builder.CreateVectorSplat(VWidth, ShiftAmt); in simplifyX86immShift()
1005 Value *ShiftAmt = ConstantInt::get(II.getType(), MaskIdx); in instCombineIntrinsic() local
1006 Value *Shifted = IC.Builder.CreateLShr(Masked, ShiftAmt); in instCombineIntrinsic()
1048 Value *ShiftAmt = ConstantInt::get(II.getType(), MaskIdx); in instCombineIntrinsic() local
1049 Value *Shifted = IC.Builder.CreateShl(Input, ShiftAmt); in instCombineIntrinsic()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp1655 MatchData.Imm = ShiftAmt; in matchCombineShlOfExtend()
1658 return MinLeadingZeros >= ShiftAmt; in matchCombineShlOfExtend()
1768 Val = Val.lshr(ShiftAmt); in matchCombineUnmergeConstant()
1996 unsigned ShiftAmt; in tryCombineShiftToUnmerge() local
2270 Register ShiftAmt; in matchCombineTruncOfShl() local
2296 Register ShiftAmt = MatchInfo.second; in applyCombineTruncOfShl() local
2758 int64_t ShiftAmt; in applyAshShlToSextInreg() local
2759 std::tie(Src, ShiftAmt) = MatchInfo; in applyAshShlToSextInreg()
3564 int64_t ShiftAmt; in getTruncStoreByteOffset() local
3577 if (ShiftAmt % NarrowBits!= 0) in getTruncStoreByteOffset()
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H A DLegalizerHelper.cpp366 auto ShiftAmt = in buildLCMMergePieces() local
1532 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, Offset); in widenScalarMergeValues() local
1662 auto Shr = MIRBuilder.buildLShr(SrcTy, SrcReg, ShiftAmt); in widenScalarUnmergeValues()
2177 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, DiffBits); in widenScalar() local
3296 auto Shifted = MIRBuilder.buildAShr(Ty, Res, ShiftAmt); in lower()
6360 auto Shift = MIRBuilder.buildShl(Src0Ty, Zext, ShiftAmt); in lowerFCopySign()
6504 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, Offset); in lowerMergeValues() local
6545 auto ShiftAmt = MIRBuilder.buildConstant(IntTy, Offset); in lowerUnmergeValues() local
7103 auto ShiftAmt = MIRBuilder.buildConstant(Ty, BaseShiftAmt); in lowerBswap() local
7288 auto ShiftAmt = in lowerAbsToAddXor() local
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/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp1825 unsigned ShiftAmt; in emitIntSExt32r1() local
1830 ShiftAmt = 24; in emitIntSExt32r1()
1833 ShiftAmt = 16; in emitIntSExt32r1()
1837 emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt); in emitIntSExt32r1()
1838 emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt); in emitIntSExt32r1()
H A DMipsISelLowering.cpp1669 Register ShiftAmt = RegInfo.createVirtualRegister(RC); in emitAtomicBinaryPartword() local
1792 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); in emitAtomicBinaryPartword()
1797 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); in emitAtomicBinaryPartword()
1802 .addReg(MaskUpper).addReg(ShiftAmt); in emitAtomicBinaryPartword()
1818 .addReg(ShiftAmt) in emitAtomicBinaryPartword()
1918 Register ShiftAmt = RegInfo.createVirtualRegister(RC); in emitAtomicCmpSwapPartword() local
1984 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); in emitAtomicCmpSwapPartword()
1989 .addReg(MaskUpper).addReg(ShiftAmt); in emitAtomicCmpSwapPartword()
1994 .addReg(MaskedCmpVal).addReg(ShiftAmt); in emitAtomicCmpSwapPartword()
1998 .addReg(MaskedNewVal).addReg(ShiftAmt); in emitAtomicCmpSwapPartword()
[all …]
/llvm-project-15.0.7/llvm/lib/ExecutionEngine/Interpreter/
H A DExecution.cpp1611 unsigned ShiftAmt = isLittleEndian ? 0 : SrcBitSize * (Ratio - 1); in executeBitCastInst() local
1617 Tmp <<= ShiftAmt; in executeBitCastInst()
1618 ShiftAmt += isLittleEndian ? SrcBitSize : -SrcBitSize; in executeBitCastInst()
1627 unsigned ShiftAmt = isLittleEndian ? 0 : DstBitSize * (Ratio - 1); in executeBitCastInst() local
1632 Elt.IntVal.lshrInPlace(ShiftAmt); in executeBitCastInst()
1636 ShiftAmt += isLittleEndian ? DstBitSize : -DstBitSize; in executeBitCastInst()

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