| /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/ |
| H A D | addc-adde-sube-subc.ll | 5 ; Ensure that the ISDOpcodes ADDC, ADDE, SUBC, SUBE are handled correctly
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| /llvm-project-15.0.7/llvm/lib/Target/Lanai/ |
| H A D | LanaiAluCode.h | 126 case ISD::SUBE: in isdToLanaiAluCode()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 280 SUBE, enumerator
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| /llvm-project-15.0.7/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1658 setOperationAction(ISD::SUBE, MVT::i32, Custom); in SparcTargetLowering()
1664 setOperationAction(ISD::SUBE, MVT::i64, Custom); in SparcTargetLowering()
3018 case ISD::SUBC: hiOpc = ISD::SUBE; break; in LowerADDC_ADDE_SUBC_SUBE()
3019 case ISD::SUBE: hasChain = true; break; in LowerADDC_ADDE_SUBC_SUBE()
3175 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); in LowerOperation()
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| H A D | SparcInstrInfo.td | 797 defm SUBE : F3_12 <"subxcc" , 0b011100, sube, IntRegs, i32, simm13Op>;
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 111 SUBE, // Sub using carry enumerator
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| H A D | ARMISelLowering.cpp | 1708 MAKE_CASE(ARMISD::SUBE) in getTargetNodeName()
6877 SDValue Cmp = DAG.getNode(ARMISD::SUBE, DL, VTs, LHS, RHS, Carry); in LowerSETCCCARRY()
9754 Result = DAG.getNode(ARMISD::SUBE, DL, VTs, Op.getOperand(0), in LowerADDSUBCARRY()
12688 AddeSubeNode->getOpcode() == ARMISD::SUBE) && in AddCombineTo64bitMLAL()
12699 (AddeSubeNode->getOpcode() == ARMISD::SUBE && in AddCombineTo64bitMLAL()
12956 unsigned Opcode = (N->getOpcode() == ARMISD::ADDE) ? ARMISD::SUBE in PerformAddeSubeCombine()
18602 case ARMISD::SUBE: return PerformAddeSubeCombine(N, DCI, Subtarget); in PerformDAGCombine()
19786 case ARMISD::SUBE: in computeKnownBitsForTargetNode()
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| H A D | ARMISelDAGToDAG.cpp | 3954 case ARMISD::SUBE: { in Select()
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| H A D | ARMInstrInfo.td | 204 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 314 case ISD::SUBE: return "sube"; in getOperationName()
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| H A D | LegalizeIntegerTypes.cpp | 186 case ISD::SUBE: in PromoteIntegerResult()
2501 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break; in ExpandIntegerResult()
2947 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps); in ExpandIntRes_ADDSUB()
3044 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps); in ExpandIntRes_ADDSUBC()
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| H A D | DAGCombiner.cpp | 1690 case ISD::SUBE: return visitSUBE(N); in visit()
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| /llvm-project-15.0.7/llvm/lib/Target/ARC/ |
| H A D | ARCISelLowering.cpp | 127 setOperationAction(ISD::SUBE, MVT::i32, Legal); in ARCTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 112 setOperationAction(ISD::SUBE, VT, Custom); in M68kTargetLowering()
1344 case ISD::SUBE: in LowerOperation()
2481 case ISD::SUBE: in LowerADDC_ADDE_SUBC_SUBE()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 536 case ISD::SUBE: { in Select()
835 bool ConsumeCarry = (Opcode == ISD::ADDE || Opcode == ISD::SUBE); in SelectADD_SUB_I64()
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| H A D | R600ISelLowering.cpp | 186 setOperationAction({ISD::ADDC, ISD::SUBC, ISD::ADDE, ISD::SUBE}, VT, in R600TargetLowering()
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| H A D | AMDGPUISelLowering.cpp | 346 setOperationAction({ISD::ADDC, ISD::SUBC, ISD::ADDE, ISD::SUBE}, VT, Legal); in AMDGPUTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 824 setOperationAction({ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}, VT, in initActions()
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| /llvm-project-15.0.7/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 527 setOperationAction(ISD::SUBE, MVT::i32, Legal); in NVPTXTargetLowering()
532 setOperationAction(ISD::SUBE, MVT::i64, Legal); in NVPTXTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 73 setOperationAction(ISD::SUBE, VT, Legal); in AVRTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 145 ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}) { in WebAssemblyTargetLowering()
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| /llvm-project-15.0.7/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 411 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 239 setOperationAction(ISD::SUBE, VT, Legal); in PPCTargetLowering()
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