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Searched refs:SETULE (Results 1 – 25 of 52) sorted by relevance

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/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1439 SETULE, // 1 1 0 1 True if unordered, less than, or equal enumerator
1464 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DAnalysis.cpp202 case FCmpInst::FCMP_ULE: return ISD::SETULE; in getFCmpCondCode()
214 case ISD::SETOLE: case ISD::SETULE: return ISD::SETLE; in getFCmpCodeWithoutNaN()
226 case ICmpInst::ICMP_ULE: return ISD::SETULE; in getICmpCondCode()
246 case ISD::SETULE: in getICmpCondCode()
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchFloat32InstrInfo.td157 // SETOGT/SETOGE/SETUGT/SETUGE will expand into SETOLT/SETOLE/SETULT/SETULE.
165 def : PatFPSetcc<SETULE, FCMP_CULE_S, FPR32>;
190 def : PatFPSelectcc<SETULE, FCMP_CULE_S, FSEL_S, FPR32>;
H A DLoongArchFloat64InstrInfo.td161 // SETOGT/SETOGE/SETUGT/SETUGE will expand into SETOLT/SETOLE/SETULT/SETULE.
169 def : PatFPSetcc<SETULE, FCMP_CULE_D, FPR64>;
190 def : PatFPSelectcc<SETULE, FCMP_CULE_D, FSEL_D, FPR64>;
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEISelDAGToDAG.cpp46 case ISD::SETULE: in intCondCode2Icc()
92 case ISD::SETULE: in fpCondCode2Fcc()
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp583 case ISD::SETULE: in NegateCC()
796 SET_NEWCC(SETULE, JULE); in EmitInstrWithCustomInserter()
H A DBPFInstrInfo.td103 [{return (N->getZExtValue() == ISD::SETULE);}]>;
123 [{return (N->getZExtValue() == ISD::SETULE);}]>;
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInteger.td81 defm LE_U : ComparisonInt<SETULE, "le_u", 0x4d, 0x58>;
H A DWebAssemblyISelLowering.cpp120 ISD::SETULT, ISD::SETULE, ISD::SETUGT, ISD::SETUGE}) in WebAssemblyTargetLowering()
244 for (auto CC : {ISD::SETUGT, ISD::SETUGE, ISD::SETULT, ISD::SETULE}) in WebAssemblyTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp3290 case ISD::SETULE: { in get32BitZExtCompare()
3463 case ISD::SETULE: { in get32BitSExtCompare()
3622 case ISD::SETULE: { in get64BitZExtCompare()
3785 case ISD::SETULE: { in get64BitSExtCompare()
4066 case ISD::SETULE: in SelectCC()
4093 case ISD::SETULE: in SelectCC()
4133 case ISD::SETULE: in getPredicateForSetCC()
4166 case ISD::SETULE: in getCRIdxForSetCC()
4198 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break; in getVCmpInst()
4206 case ISD::SETULE: CC = ISD::SETOGT; Negate = true; break; in getVCmpInst()
[all …]
H A DPPCInstrInfo.td3341 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)),
3648 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)),
3665 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)),
3677 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)),
3694 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)),
3707 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)),
3779 defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETULE)),
3806 defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETULE)),
3832 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULE)),
3861 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULE)),
[all …]
H A DPPCInstrSPE.td844 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULE)),
865 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULE)),
H A DPPCInstrP10.td1864 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)),
1875 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETULE)),
1890 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)),
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVSDPatterns.td693 defm : VPatIntegerSetCCSDNode_VV_Swappable<"PseudoVMSLEU", SETULE, SETUGE>;
700 defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSLEU", SETULE, SETUGE>;
708 defm : VPatIntegerSetCCSDNode_VI<"PseudoVMSLEU", SETULE>;
H A DRISCVInstrInfoVVLPatterns.td1069 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>;
1076 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>;
1084 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>;
1094 defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSGTU", SETUGE, SETULE,
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp381 case ISD::SETULE: in softenSetCCOperands()
3779 } else if (Cond == ISD::CondCode::SETULE) { in optimizeSetCCOfSignedTruncationCheck()
4373 case ISD::SETULE: in SimplifySetCC()
4396 case ISD::SETULE: { in SimplifySetCC()
4591 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { in SimplifySetCC()
4731 (Cond == ISD::SETULE && C1.isMaxSignedValue())) in SimplifySetCC()
4800 Cond == ISD::SETULE || Cond == ISD::SETUGT) { in SimplifySetCC()
4801 bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT); in SimplifySetCC()
5016 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y in SimplifySetCC()
6328 DAG.getSetCC(DL, SETCCVT, D, CompTargetNode, ISD::SETULE); in prepareUREMEqFold()
[all …]
H A DSelectionDAGDumper.cpp459 case ISD::SETULE: return "setule"; in getOperationName()
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp50 case ISD::SETULE: in ISDCCtoARCCC()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp954 case ISD::SETULE: in isLegalDSPCondCode()
1734 Op->getOperand(2), ISD::SETULE); in lowerINTRINSIC_WO_CHAIN()
1740 lowerMSASplatImm(Op, 2, DAG), ISD::SETULE); in lowerINTRINSIC_WO_CHAIN()
1843 Op->getOperand(2), ISD::SETULE); in lowerINTRINSIC_WO_CHAIN()
H A DMipsMSAInstrInfo.td148 def vfsetule_v4f32 : vfsetcc_type<v4i32, v4f32, SETULE>;
149 def vfsetule_v2f64 : vfsetcc_type<v2i64, v2f64, SETULE>;
174 def vsetule_v16i8 : vsetcc_type<v16i8, SETULE>;
175 def vsetule_v8i16 : vsetcc_type<v8i16, SETULE>;
176 def vsetule_v4i32 : vsetcc_type<v4i32, SETULE>;
177 def vsetule_v2i64 : vsetcc_type<v2i64, SETULE>;
H A DMipsDSPInstrInfo.td1420 def : DSPSetCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>;
1433 def : DSPSelectCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>;
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructions.td343 def COND_ULE : PatFrag<(ops), (OtherVT SETULE)>;
H A DR600ISelLowering.cpp88 ISD::SETUGT, ISD::SETULT, ISD::SETULE}, in R600TargetLowering()
91 setCondCodeAction({ISD::SETLE, ISD::SETLT, ISD::SETULE, ISD::SETULT}, in R600TargetLowering()
H A DSIWholeQuadMode.cpp842 case ISD::SETULE: in lowerKillF32()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp232 setCondCodeAction(ISD::SETULE, T, Expand); in initializeHVXLowering()
305 setCondCodeAction(ISD::SETULE, MVT::v64f16, Expand); in initializeHVXLowering()
318 setCondCodeAction(ISD::SETULE, MVT::v32f32, Expand); in initializeHVXLowering()

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