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Searched refs:SETUGT (Results 1 – 25 of 53) sorted by relevance

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/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1436 SETUGT, // 1 0 1 0 True if unordered or greater than enumerator
1464 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DAnalysis.cpp199 case FCmpInst::FCMP_UGT: return ISD::SETUGT; in getFCmpCondCode()
215 case ISD::SETOGT: case ISD::SETUGT: return ISD::SETGT; in getFCmpCodeWithoutNaN()
232 case ICmpInst::ICMP_UGT: return ISD::SETUGT; in getICmpCondCode()
258 case ISD::SETUGT: in getICmpCondCode()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEISelDAGToDAG.cpp48 case ISD::SETUGT: in intCondCode2Icc()
90 case ISD::SETUGT: in fpCondCode2Fcc()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp3305 case ISD::SETUGT: in get32BitZExtCompare()
3478 case ISD::SETUGT: in get32BitSExtCompare()
3634 case ISD::SETUGT: in get64BitZExtCompare()
3797 case ISD::SETUGT: in get64BitSExtCompare()
4065 case ISD::SETUGT: in SelectCC()
4092 case ISD::SETUGT: in SelectCC()
4146 case ISD::SETUGT: return PPC::PRED_GT; in getPredicateForSetCC()
4178 case ISD::SETUGT: return 1; in getCRIdxForSetCC()
4281 case ISD::SETUGT: in getVCmpInst()
4575 if (InnerCC == ISD::SETULT || InnerCC == ISD::SETUGT) { in mayUseP9Setb()
[all …]
H A DPPCInstrInfo.td3376 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)),
3383 // SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
3567 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)),
3595 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)),
3607 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)),
3635 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)),
3847 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGT)),
3871 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGT)),
3892 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGT)),
3914 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)),
[all …]
H A DPPCInstrSPE.td854 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)),
875 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGT)),
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInteger.td79 defm GT_U : ComparisonInt<SETUGT, "gt_u", 0x4b, 0x56>;
H A DWebAssemblyISelLowering.cpp120 ISD::SETULT, ISD::SETULE, ISD::SETUGT, ISD::SETUGE}) in WebAssemblyTargetLowering()
244 for (auto CC : {ISD::SETUGT, ISD::SETUGE, ISD::SETULT, ISD::SETULE}) in WebAssemblyTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVSDPatterns.td691 defm : VPatIntegerSetCCSDNode_VV_Swappable<"PseudoVMSLTU", SETULT, SETUGT>;
698 defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSLTU", SETULT, SETUGT>;
702 defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSGTU", SETUGT, SETULT>;
710 defm : VPatIntegerSetCCSDNode_VI<"PseudoVMSGTU", SETUGT>;
H A DRISCVInstrInfoVVLPatterns.td1067 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLTU", SETULT, SETUGT>;
1074 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLTU", SETULT, SETUGT>;
1078 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSGTU", SETUGT, SETULT>;
1086 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGTU", SETUGT, SETULT>;
1090 defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSLEU", SETULT, SETUGT,
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchFloat32InstrInfo.td157 // SETOGT/SETOGE/SETUGT/SETUGE will expand into SETOLT/SETOLE/SETULT/SETULE.
H A DLoongArchFloat64InstrInfo.td161 // SETOGT/SETOGE/SETUGT/SETUGE will expand into SETOLT/SETOLE/SETULT/SETULE.
H A DLoongArchISelLowering.cpp69 ISD::SETUGT, ISD::SETUGE}; in LoongArchTargetLowering()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp386 case ISD::SETUGT: in softenSetCCOperands()
3783 } else if (Cond == ISD::CondCode::SETUGT) { in optimizeSetCCOfSignedTruncationCheck()
3978 if (Cond == ISD::SETULT || Cond == ISD::SETUGT) { in simplifySetCCWithCTPOP()
4368 case ISD::SETUGT: in SimplifySetCC()
4393 case ISD::SETUGT: in SimplifySetCC()
4629 if (Cond == ISD::SETGT || Cond == ISD::SETUGT) { in SimplifySetCC()
4722 if ((Cond == ISD::SETUGT && C1.isMaxSignedValue()) || in SimplifySetCC()
8847 case ISD::UMAX: CC = ISD::SETUGT; break; in expandIntMINMAX()
9084 ISD::SETUGT); in expandFixedPointMul()
9246 ISD::CondCode CC = IsAdd ? ISD::SETULT : ISD::SETUGT; in expandUADDSUBO()
[all …]
H A DSelectionDAGDumper.cpp456 case ISD::SETUGT: return "setugt"; in getOperationName()
H A DLegalizeIntegerTypes.cpp2854 return std::make_pair(ISD::SETUGT, ISD::UMAX); in getExpandedMinMaxOps()
3091 Cond = ISD::SETUGT; in ExpandIntRes_UADDSUBO()
3916 SDValue HLUGT = DAG.getSetCC(dl, BoolNVT, ResultHL, HLLoMask, ISD::SETUGT); in ExpandIntRes_MULFIX()
4800 case ISD::SETUGT: LowCC = ISD::SETUGT; break; in IntegerExpandSetCCOperands()
4870 case ISD::SETUGT: CCCode = ISD::SETULT; FlipOperands = true; break; in IntegerExpandSetCCOperands()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp259 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); in MipsSETargetLowering()
264 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand); in MipsSETargetLowering()
360 setCondCodeAction(ISD::SETUGT, Ty, Expand); in addMSAIntType()
396 setCondCodeAction(ISD::SETUGT, Ty, Expand); in addMSAFloatType()
955 case ISD::SETUGT: in isLegalDSPCondCode()
H A DMipsDSPInstrInfo.td1423 def : DSPSetCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;
1436 def : DSPSelectCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFInstrInfo.td93 [{return (N->getZExtValue() == ISD::SETUGT);}]>;
113 [{return (N->getZExtValue() == ISD::SETUGT);}]>;
H A DBPFISelLowering.cpp788 SET_NEWCC(SETUGT, JUGT); in EmitInstrWithCustomInserter()
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp44 case ISD::SETUGT: in ISDCCtoARCCC()
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1513 case ISD::SETUGT: in TranslateIntegerM68kCC()
1560 case ISD::SETUGT: in TranslateM68kCC()
1586 case ISD::SETUGT: // flipped in TranslateM68kCC()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructions.td340 def COND_UGT : PatFrag<(ops), (OtherVT SETUGT)>;
H A DSIWholeQuadMode.cpp833 case ISD::SETUGT: in lowerKillF32()
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYISelLowering.cpp112 ISD::SETONE, ISD::SETUEQ, ISD::SETUGT, in CSKYTargetLowering()

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