| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsTargetTransformInfo.cpp | 15 return TLI->isOperationLegalOrCustom(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, in hasDivRemOp()
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| H A D | MipsSEISelLowering.cpp | 191 setOperationAction(ISD::SDIVREM, MVT::i64, Custom); in MipsSETargetLowering()
198 setOperationAction(ISD::SDIVREM, MVT::i32, Custom); in MipsSETargetLowering()
231 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in MipsSETargetLowering()
278 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); in MipsSETargetLowering()
452 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG); in LowerOperation()
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| H A D | MipsISelLowering.cpp | 483 setTargetDAGCombine({ISD::SDIVREM, ISD::UDIVREM, ISD::SELECT, ISD::AND, in MipsTargetLowering()
556 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 : in performDivRemCombine()
1152 case ISD::SDIVREM: in PerformDAGCombine()
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| /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/ |
| H A D | divrem.ll | 3 ; SDIVREM/UDIVREM DAG nodes are generated but expanded when lowering and
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 255 SDIVREM, enumerator
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| H A D | BasicTTIImpl.h | 828 if (TLI->isOperationLegalOrCustom(IsSigned ? ISD::SDIVREM : ISD::UDIVREM,
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| /llvm-project-15.0.7/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 159 setOperationAction(ISD::SDIVREM, MVT::i8, Custom); in AVRTargetLowering()
160 setOperationAction(ISD::SDIVREM, MVT::i16, Custom); in AVRTargetLowering()
161 setOperationAction(ISD::SDIVREM, MVT::i32, Custom); in AVRTargetLowering()
472 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) && in LowerDivRem()
474 bool IsSigned = (Opcode == ISD::SDIVREM); in LowerDivRem()
861 case ISD::SDIVREM: in LowerOperation()
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| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.h | 94 SDIVREM, enumerator
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| H A D | SystemZOperators.td | 273 def z_sdivrem : SDNode<"SystemZISD::SDIVREM", SDT_ZGR128Binary>;
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| H A D | SystemZISelLowering.cpp | 176 setOperationAction(ISD::SDIVREM, VT, Custom); in SystemZTargetLowering()
3876 lowerGR128Binary(DAG, DL, VT, SystemZISD::SDIVREM, Op0, Op1, Ops[1], Ops[0]); in lowerSDIVREM()
5733 case ISD::SDIVREM: in LowerOperation()
5930 OPCODE(SDIVREM); in getTargetNodeName()
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| /llvm-project-15.0.7/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 136 setOperationAction(ISD::SDIVREM, MVT::i8, Promote); in MSP430TargetLowering()
142 setOperationAction(ISD::SDIVREM, MVT::i16, Expand); in MSP430TargetLowering()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 245 case ISD::SDIVREM: return "sdivrem"; in getOperationName()
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| H A D | LegalizeVectorOps.cpp | 324 case ISD::SDIVREM: in LegalizeOp()
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| H A D | LegalizeIntegerTypes.cpp | 4119 if (TLI.getOperationAction(ISD::SDIVREM, VT) == TargetLowering::Custom) { in ExpandIntRes_SDIV()
4120 SDValue Res = DAG.getNode(ISD::SDIVREM, dl, DAG.getVTList(VT, VT), Ops); in ExpandIntRes_SDIV()
4318 if (TLI.getOperationAction(ISD::SDIVREM, VT) == TargetLowering::Custom) { in ExpandIntRes_SREM()
4319 SDValue Res = DAG.getNode(ISD::SDIVREM, dl, DAG.getVTList(VT, VT), Ops); in ExpandIntRes_SREM()
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| H A D | LegalizeDAG.cpp | 2155 bool isSigned = Opcode == ISD::SDIVREM; in ExpandDivRemLibCall()
3304 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; in ExpandNode()
4401 case ISD::SDIVREM: in ConvertNodeToLibcall()
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| /llvm-project-15.0.7/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 103 setOperationAction(ISD::SDIVREM, VT, Expand); in BPFTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 338 setOperationAction({ISD::SDIVREM, ISD::UDIVREM}, VT, Custom); in AMDGPUTargetLowering()
383 ISD::UMUL_LOHI, ISD::SDIVREM, ISD::UDIVREM, in AMDGPUTargetLowering()
1154 case ISD::SDIVREM: return LowerSDIVREM(Op, DAG); in LowerOperation()
1978 SDValue DIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(HalfVT, HalfVT), in LowerSDIVREM()
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| H A D | R600ISelLowering.cpp | 604 case ISD::SDIVREM: { in ReplaceNodeResults()
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| /llvm-project-15.0.7/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 61 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in CSKYTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 108 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in LanaiTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 204 setOperationAction(ISD::SDIVREM, VT, Expand); in addTypeForNEON()
287 setOperationAction(ISD::SDIVREM, VT, Expand); in addMVEVectorTypes()
1274 setOperationAction(ISD::SDIVREM, MVT::i32, Custom); in ARMTargetLowering()
1276 setOperationAction(ISD::SDIVREM, MVT::i64, Custom); in ARMTargetLowering()
1279 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in ARMTargetLowering()
10438 case ISD::SDIVREM: in LowerOperation()
10511 case ISD::SDIVREM: in ReplaceNodeResults()
20380 bool isSigned = N->getOpcode() == ISD::SDIVREM || in getDivRemLibcall()
20398 bool isSigned = N->getOpcode() == ISD::SDIVREM || in getDivRemArgList()
20422 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) && in LowerDivRem()
[all …]
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| H A D | ARMTargetTransformInfo.cpp | 1929 case ISD::SDIVREM: in maybeLoweredToCall()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1582 ISD::SDIVREM, ISD::UDIVREM, ISD::ROTL, ISD::ROTR, in HexagonTargetLowering()
1628 ISD::SREM, ISD::UREM, ISD::SDIVREM, ISD::UDIVREM, ISD::SADDO, in HexagonTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1596 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in SparcTargetLowering()
1603 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); in SparcTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 144 ISD::SDIVREM, ISD::UDIVREM, ISD::SHL_PARTS, ISD::SRA_PARTS, in WebAssemblyTargetLowering()
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