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Searched refs:ROTR (Results 1 – 25 of 52) sorted by relevance

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/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/
H A Dbswap.mir22 ; MIPS32R2: [[ROTR:%[0-9]+]]:gpr32 = ROTR [[WSBH]], 16
23 ; MIPS32R2: $v0 = COPY [[ROTR]]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dprelegalizercombiner-funnel-shifts-to-rotates.mir22 ; CHECK: [[ROTR:%[0-9]+]]:_(s32) = G_ROTR [[COPY]], [[COPY1]](s32)
23 ; CHECK: $w0 = COPY [[ROTR]](s32)
78 ; CHECK: [[ROTR:%[0-9]+]]:_(<4 x s32>) = G_ROTR [[COPY]], [[COPY1]](<4 x s32>)
79 ; CHECK: $q0 = COPY [[ROTR]](<4 x s32>)
H A Dpostlegalizercombiner-rotate.mir46 ; CHECK: [[ROTR:%[0-9]+]]:_(s32) = G_ROTR [[COPY]], [[C]](s64)
47 ; CHECK: $w0 = COPY [[ROTR]](s32)
H A Dmerge-stores-truncating.mir127 ; CHECK-NEXT: [[ROTR:%[0-9]+]]:_(s32) = G_ROTR [[COPY]], [[C]](s32)
128 ; CHECK-NEXT: G_STORE [[ROTR]](s32), [[COPY1]](p0) :: (store (s32), align 2)
160 ; CHECK-NEXT: [[ROTR:%[0-9]+]]:_(s32) = G_ROTR [[COPY]], [[C]](s32)
161 ; CHECK-NEXT: G_STORE [[ROTR]](s32), [[COPY1]](p0) :: (store (s32), align 2)
334 ; CHECK-NEXT: [[ROTR:%[0-9]+]]:_(s64) = G_ROTR [[COPY]], [[C]](s64)
335 ; CHECK-NEXT: G_STORE [[ROTR]](s64), [[COPY1]](p0) :: (store (s64), align 4)
367 ; CHECK-NEXT: [[ROTR:%[0-9]+]]:_(s64) = G_ROTR [[COPY]], [[C]](s64)
368 ; CHECK-NEXT: G_STORE [[ROTR]](s64), [[COPY1]](p0) :: (store (s64), align 4)
/llvm-project-15.0.7/llvm/lib/Support/
H A DSHA256.cpp36 #define ROTR(x, n) (((x) >> n) | ((x) << (32 - (n)))) macro
41 #define SIGMA_0(x) (ROTR(x, 2) ^ ROTR(x, 13) ^ ROTR(x, 22))
42 #define SIGMA_1(x) (ROTR(x, 6) ^ ROTR(x, 11) ^ ROTR(x, 25))
44 #define SIGMA_2(x) (ROTR(x, 17) ^ ROTR(x, 19) ^ SHR(x, 10))
45 #define SIGMA_3(x) (ROTR(x, 7) ^ ROTR(x, 18) ^ SHR(x, 3))
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.h29 case ISD::ROTR: return ARM_AM::ror; in getShiftOpcForNode()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp3553 { ISD::ROTR, MVT::v32i16, 2 }, in getIntrinsicInstrCost()
3554 { ISD::ROTR, MVT::v16i16, 2 }, in getIntrinsicInstrCost()
3555 { ISD::ROTR, MVT::v8i16, 2 }, in getIntrinsicInstrCost()
3556 { ISD::ROTR, MVT::v64i8, 5 }, in getIntrinsicInstrCost()
3557 { ISD::ROTR, MVT::v32i8, 5 }, in getIntrinsicInstrCost()
3558 { ISD::ROTR, MVT::v16i8, 5 } in getIntrinsicInstrCost()
3567 { ISD::ROTR, MVT::v8i64, 1 }, in getIntrinsicInstrCost()
3568 { ISD::ROTR, MVT::v4i64, 1 }, in getIntrinsicInstrCost()
3572 { ISD::ROTR, MVT::v4i32, 1 } in getIntrinsicInstrCost()
3591 { ISD::ROTR, MVT::v16i8, 2 } in getIntrinsicInstrCost()
[all …]
H A DX86InstrShiftRotate.td862 // Convert a ROTL shamt to a ROTR shamt on 32-bit integer.
867 // Convert a ROTL shamt to a ROTR shamt on 64-bit integer.
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h695 ROTR, enumerator
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMips16ISelLowering.cpp144 setOperationAction(ISD::ROTR, MVT::i32, Expand); in Mips16TargetLowering()
145 setOperationAction(ISD::ROTR, MVT::i64, Expand); in Mips16TargetLowering()
H A DMipsScheduleP5600.td224 def : InstRW<[P5600WriteEitherALU], (instrs ADD, ADDi, ADDiu, ANDi, ORi, ROTR,
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp95 setOperationAction(ISD::ROTR, MVT::i8, Custom); in AVRTargetLowering()
96 setOperationAction(ISD::ROTR, MVT::i16, Expand); in AVRTargetLowering()
298 case ISD::ROTR: { in LowerShifts()
322 case ISD::ROTR: in LowerShifts()
847 case ISD::ROTR: in LowerOperation()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInteger.td70 defm ROTR : BinaryInt<rotr, "rotr", 0x78, 0x8a>;
/llvm-project-15.0.7/llvm/unittests/CodeGen/GlobalISel/
H A DLegalizerHelperTest.cpp40 auto ROTR = B.buildInstr(TargetOpcode::G_ROTR, {S32}, {Src, Amt}); in TEST_F() local
48 Helper.lower(*ROTR, 0, S32)); in TEST_F()
93 auto ROTR = B.buildInstr(TargetOpcode::G_ROTR, {S24}, {Src, Amt}); in TEST_F() local
101 Helper.lower(*ROTR, 0, S24)); in TEST_F()
153 auto ROTR = B.buildInstr(TargetOpcode::G_ROTR, {V4S32}, {Src, Amt}); in TEST_F() local
160 Helper.lower(*ROTR, 0, V4S32)); in TEST_F()
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dlogical_shifted_reg.ll230 ; operations. DAGCombiner should ensure we the ROTR during
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp82 setOperationAction(ISD::ROTR, MVT::i8, Expand); in MSP430TargetLowering()
84 setOperationAction(ISD::ROTR, MVT::i16, Expand); in MSP430TargetLowering()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp340 case ISD::ROTR: in LegalizeOp()
807 case ISD::ROTR: in Expand()
H A DSelectionDAGDumper.cpp254 case ISD::ROTR: return "rotr"; in getOperationName()
H A DTargetLowering.cpp2031 case ISD::ROTR: { in SimplifyDemandedBits()
3346 case ISD::ROTR: { in SimplifyDemandedVectorElts()
4033 if (X.getOpcode() == ISD::ROTL || X.getOpcode() == ISD::ROTR) in foldSetCCWithRotate()
6303 if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::ROTR, VT)) in prepareUREMEqFold()
6306 Op0 = DAG.getNode(ISD::ROTR, DL, VT, Op0, KVal); in prepareUREMEqFold()
6568 if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::ROTR, VT)) in prepareSREMEqFold()
6571 Op0 = DAG.getNode(ISD::ROTR, DL, VT, Op0, KVal); in prepareSREMEqFold()
7232 unsigned RevRot = IsLeft ? ISD::ROTR : ISD::ROTL; in expandROT()
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp110 setOperationAction(ISD::ROTR, VT, Expand); in BPFTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp133 setOperationAction(ISD::ROTR, MVT::i32, Legal); in ARCTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1582 ISD::SDIVREM, ISD::UDIVREM, ISD::ROTL, ISD::ROTR, in HexagonTargetLowering()
1631 ISD::AND, ISD::OR, ISD::XOR, ISD::ROTL, ISD::ROTR, in HexagonTargetLowering()
1799 setOperationAction(ISD::ROTR, MVT::i32, Legal); in HexagonTargetLowering()
1800 setOperationAction(ISD::ROTR, MVT::i64, Legal); in HexagonTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp443 setOperationAction(ISD::ROTR, MVT::i64, Legal); in NVPTXTargetLowering()
445 setOperationAction(ISD::ROTR, MVT::i32, Legal); in NVPTXTargetLowering()
448 setOperationAction(ISD::ROTR, MVT::i16, Expand); in NVPTXTargetLowering()
450 setOperationAction(ISD::ROTR, MVT::i8, Expand); in NVPTXTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp248 setOperationAction({ISD::ROTL, ISD::ROTR}, MVT::i32, Custom); in RISCVTargetLowering()
250 setOperationAction({ISD::ROTL, ISD::ROTR}, XLenVT, Expand); in RISCVTargetLowering()
557 setOperationAction({ISD::ROTL, ISD::ROTR}, VT, Expand); in RISCVTargetLowering()
950 setTargetDAGCombine({ISD::ROTL, ISD::ROTR}); in RISCVTargetLowering()
6801 case ISD::ROTR: in getRISCVWOpcode()
6983 case ISD::ROTR: in ReplaceNodeResults()
7671 Reverse.getOpcode() == ISD::ROTR) && in combineORToGORC()
7866 assert((N->getOpcode() == ISD::ROTR || N->getOpcode() == ISD::ROTL || in combineROTR_ROTL_RORW_ROLW()
8898 case ISD::ROTR: in PerformDAGCombine()
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYISelLowering.cpp64 setOperationAction(ISD::ROTR, MVT::i32, Expand); in CSKYTargetLowering()

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