| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.h | 192 bool isSGPRClassID(unsigned RCID) const { in isSGPRClassID() argument
193 return isSGPRClass(getRegClass(RCID)); in isSGPRClassID()
349 const TargetRegisterClass *getRegClass(unsigned RCID) const;
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| H A D | AMDGPUTargetTransformInfo.h | 115 unsigned getNumberOfRegisters(unsigned RCID) const;
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| H A D | SIInstrInfo.cpp | 4775 switch (RCID) { in adjustAllocatableRegClass()
4777 RCID = AMDGPU::VGPR_32RegClassID; in adjustAllocatableRegClass()
4780 RCID = AMDGPU::VReg_64RegClassID; in adjustAllocatableRegClass()
4783 RCID = AMDGPU::VReg_96RegClassID; in adjustAllocatableRegClass()
4786 RCID = AMDGPU::VReg_128RegClassID; in adjustAllocatableRegClass()
4789 RCID = AMDGPU::VReg_160RegClassID; in adjustAllocatableRegClass()
4792 RCID = AMDGPU::VReg_512RegClassID; in adjustAllocatableRegClass()
4799 return RI.getProperlyAlignedRC(RI.getRegClass(RCID)); in adjustAllocatableRegClass()
4846 unsigned RCID = Desc.OpInfo[OpNo].RegClass; in getOpRegClass() local
4856 const TargetRegisterClass *RC = RI.getRegClass(RCID); in legalizeOpWithMove()
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| H A D | SIRegisterInfo.cpp | 2947 SIRegisterInfo::getRegClass(unsigned RCID) const { in getRegClass()
2948 switch ((int)RCID) { in getRegClass()
2957 return AMDGPUGenRegisterInfo::getRegClass(RCID); in getRegClass()
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| H A D | AMDGPUTargetTransformInfo.cpp | 297 unsigned GCNTTIImpl::getNumberOfRegisters(unsigned RCID) const { in getNumberOfRegisters()
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| H A D | AMDGPUISelDAGToDAG.cpp | 390 unsigned RCID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); in getOperandRegClass() local
392 Subtarget->getRegisterInfo()->getRegClass(RCID); in getOperandRegClass()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | MachineInstr.cpp | 858 unsigned RCID; in getRegClassConstraint() local
862 InlineAsm::hasRegClassConstraint(Flag, RCID)) in getRegClassConstraint()
863 return TRI->getRegClass(RCID); in getRegClassConstraint()
1692 unsigned RCID = 0; in print() local
1694 InlineAsm::hasRegClassConstraint(Flag, RCID)) { in print()
1696 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID)); in print()
1698 OS << ":RC" << RCID; in print()
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| H A D | TargetInstrInfo.cpp | 1381 unsigned RCID = 0; in createMIROperandComment() local
1383 InlineAsm::hasRegClassConstraint(Flag, RCID)) { in createMIROperandComment()
1385 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID)); in createMIROperandComment()
1387 OS << ":RC" << RCID; in createMIROperandComment()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/Utils/ |
| H A D | AMDGPUBaseInfo.cpp | 1980 unsigned getRegBitWidth(unsigned RCID) { in getRegBitWidth() argument
1981 switch (RCID) { in getRegBitWidth()
2092 unsigned RCID = Desc.OpInfo[OpNo].RegClass; in getRegOperandSize() local
2093 return getRegBitWidth(MRI->getRegClass(RCID)) / 8; in getRegOperandSize()
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| H A D | AMDGPUBaseInfo.h | 875 unsigned getRegBitWidth(unsigned RCID);
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 255 bool isRegOrInline(unsigned RCID, MVT type) const { in isRegOrInline() argument
256 return isRegClass(RCID) || isInlinableImm(type); in isRegOrInline()
259 bool isRegOrImmWithInputMods(unsigned RCID, MVT type) const { in isRegOrImmWithInputMods() argument
260 return isRegOrInline(RCID, type) || isLiteralImm(type); in isRegOrImmWithInputMods()
397 bool isRegClass(unsigned RCID) const;
401 bool isRegOrInlineNoMods(unsigned RCID, MVT type) const { in isRegOrInlineNoMods() argument
402 return isRegOrInline(RCID, type) && !hasModifiers(); in isRegOrInlineNoMods()
2018 bool AMDGPUOperand::isRegClass(unsigned RCID) const { in isRegClass()
2625 int RCID = getRegClass(RegKind, RegWidth); in getRegularReg() local
2626 if (RCID == -1) { in getRegularReg()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| H A D | AMDGPUInstPrinter.cpp | 748 int RCID = Desc.OpInfo[OpNo].RegClass; in printRegularOperand() local
749 unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID)); in printRegularOperand()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86FloatingPoint.cpp | 1596 unsigned RCID; in handleSpecialFP() local
1614 if (InlineAsm::hasRegClassConstraint(Flags, RCID)) { in handleSpecialFP()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 161 unsigned RCID = getRegClassIDForVecVT(ContainerVT); in RISCVTargetLowering() local
163 addRegisterClass(VT, TRI.getRegClass(RCID)); in RISCVTargetLowering()
1541 for (const unsigned RCID : in decomposeSubvectorInsertExtractToSubRegs()
1543 if (VecRegClassID > RCID && SubRegClassID <= RCID) { in decomposeSubvectorInsertExtractToSubRegs()
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