255   bool isRegOrInline(unsigned RCID, MVT type) const {  in isRegOrInline()  argument
256     return isRegClass(RCID) || isInlinableImm(type);  in isRegOrInline()
259   bool isRegOrImmWithInputMods(unsigned RCID, MVT type) const {  in isRegOrImmWithInputMods()  argument
260     return isRegOrInline(RCID, type) || isLiteralImm(type);  in isRegOrImmWithInputMods()
397   bool isRegClass(unsigned RCID) const;
401   bool isRegOrInlineNoMods(unsigned RCID, MVT type) const {  in isRegOrInlineNoMods()  argument
402     return isRegOrInline(RCID, type) && !hasModifiers();  in isRegOrInlineNoMods()
2018 bool AMDGPUOperand::isRegClass(unsigned RCID) const {  in isRegClass()
2019   return isRegKind() && AsmParser->getMRI()->getRegClass(RCID).contains(getReg());  in isRegClass()
2625   int RCID = getRegClass(RegKind, RegWidth);  in getRegularReg()  local
2626   if (RCID == -1) {  in getRegularReg()
2632   const MCRegisterClass RC = TRI->getRegClass(RCID);  in getRegularReg()