Lines Matching refs:RCID
4769 const MCInstrDesc &TID, unsigned RCID, in adjustAllocatableRegClass() argument
4775 switch (RCID) { in adjustAllocatableRegClass()
4777 RCID = AMDGPU::VGPR_32RegClassID; in adjustAllocatableRegClass()
4780 RCID = AMDGPU::VReg_64RegClassID; in adjustAllocatableRegClass()
4783 RCID = AMDGPU::VReg_96RegClassID; in adjustAllocatableRegClass()
4786 RCID = AMDGPU::VReg_128RegClassID; in adjustAllocatableRegClass()
4789 RCID = AMDGPU::VReg_160RegClassID; in adjustAllocatableRegClass()
4792 RCID = AMDGPU::VReg_512RegClassID; in adjustAllocatableRegClass()
4799 return RI.getProperlyAlignedRC(RI.getRegClass(RCID)); in adjustAllocatableRegClass()
4846 unsigned RCID = Desc.OpInfo[OpNo].RegClass; in getOpRegClass() local
4847 return adjustAllocatableRegClass(ST, RI, MRI, Desc, RCID, true); in getOpRegClass()
4855 unsigned RCID = get(MI.getOpcode()).OpInfo[OpIdx].RegClass; in legalizeOpWithMove() local
4856 const TargetRegisterClass *RC = RI.getRegClass(RCID); in legalizeOpWithMove()
7763 const auto RCID = MI.getDesc().OpInfo[Idx].RegClass; in isBufferSMRD() local
7764 return RI.getRegClass(RCID)->hasSubClassEq(&AMDGPU::SGPR_128RegClass); in isBufferSMRD()