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/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyExplicitLocals.cpp89 if (RC == &WebAssembly::I32RegClass) in getDropOpcode()
91 if (RC == &WebAssembly::I64RegClass) in getDropOpcode()
93 if (RC == &WebAssembly::F32RegClass) in getDropOpcode()
95 if (RC == &WebAssembly::F64RegClass) in getDropOpcode()
108 if (RC == &WebAssembly::I32RegClass) in getLocalGetOpcode()
110 if (RC == &WebAssembly::I64RegClass) in getLocalGetOpcode()
112 if (RC == &WebAssembly::F32RegClass) in getLocalGetOpcode()
114 if (RC == &WebAssembly::F64RegClass) in getLocalGetOpcode()
127 if (RC == &WebAssembly::I32RegClass) in getLocalSetOpcode()
129 if (RC == &WebAssembly::I64RegClass) in getLocalSetOpcode()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonBitTracker.cpp93 unsigned ID = RC.getID(); in mask()
119 if (RC.contains(Reg)) in getPhysRegBitWidth()
133 return RC; in composeWithSubRegIndex()
142 switch (RC.getID()) { in composeWithSubRegIndex()
278 return eXTR(RC, 0, RW); in evaluate()
283 uint16_t W = RC.width(); in evaluate()
304 return RC; in evaluate()
696 RC[BX] = RC[BX].is(0) ? BT::BitValue::One in evaluate()
798 RegisterCell RC(WR); in evaluate() local
894 RegisterCell RC(W0); in evaluate() local
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H A DBitTracker.h327 return !operator==(RC);
365 RegisterCell RC(Width); in self()
368 return RC; in self()
373 RegisterCell RC(Width); in top()
376 return RC; in top()
382 RegisterCell RC(W); in ref()
384 RC[i] = BitValue::ref(C[i]); in ref()
385 return RC; in ref()
406 RegisterCell RC = getCell(RR, M); in getRef() local
407 return RegisterCell::ref(RC); in getRef()
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/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXRegisterInfo.cpp30 if (RC == &NVPTX::Float32RegsRegClass) in getNVPTXRegClassName()
32 if (RC == &NVPTX::Float16RegsRegClass) in getNVPTXRegClassName()
40 if (RC == &NVPTX::Float64RegsRegClass) in getNVPTXRegClassName()
42 if (RC == &NVPTX::Int64RegsRegClass) in getNVPTXRegClassName()
62 if (RC == &NVPTX::Int32RegsRegClass) in getNVPTXRegClassName()
64 if (RC == &NVPTX::Int16RegsRegClass) in getNVPTXRegClassName()
66 if (RC == &NVPTX::Int1RegsRegClass) in getNVPTXRegClassName()
82 if (RC == &NVPTX::Int64RegsRegClass) in getNVPTXRegClassStr()
84 if (RC == &NVPTX::Int32RegsRegClass) in getNVPTXRegClassStr()
86 if (RC == &NVPTX::Int16RegsRegClass) in getNVPTXRegClassStr()
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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h188 return hasSGPRs(RC) && !hasVGPRs(RC) && !hasAGPRs(RC); in isSGPRClass()
200 return hasVGPRs(RC) && !hasAGPRs(RC) && !hasSGPRs(RC); in isVGPRClass()
205 return hasAGPRs(RC) && !hasVGPRs(RC) && !hasSGPRs(RC); in isAGPRClass()
210 return hasVGPRs(RC) && hasAGPRs(RC) && !hasSGPRs(RC); in isVectorSuperClass()
215 return hasVGPRs(RC) && hasSGPRs(RC) && !hasAGPRs(RC); in isVSSuperClass()
219 static bool hasVGPRs(const TargetRegisterClass *RC) { in hasVGPRs() argument
220 return RC->TSFlags & SIRCFlags::HasVGPR; in hasVGPRs()
225 return RC->TSFlags & SIRCFlags::HasAGPR; in hasAGPRs()
230 return RC->TSFlags & SIRCFlags::HasSGPR; in hasSGPRs()
235 return hasVGPRs(RC) || hasAGPRs(RC); in hasVectorRegisters()
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/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrFMA.td40 (ins RC:$src1, RC:$src2, RC:$src3),
43 [(set RC:$dst, (VT (Op RC:$src2, RC:$src1, RC:$src3)))]>,
51 [(set RC:$dst, (VT (Op RC:$src2, RC:$src1,
61 (ins RC:$src1, RC:$src2, RC:$src3),
81 (ins RC:$src1, RC:$src2, RC:$src3),
182 (ins RC:$src1, RC:$src2, RC:$src3),
185 [(set RC:$dst, (OpNode RC:$src2, RC:$src1, RC:$src3))]>,
203 (ins RC:$src1, RC:$src2, RC:$src3),
223 (ins RC:$src1, RC:$src2, RC:$src3),
395 (ins RC:$src1, RC:$src2, RC:$src3),
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H A DX86InstrAVX512.td705 Cast.RC:$src0, Cast.KRCWM:$mask, To.RC:$src1, From.RC:$src2,
1771 (ins _.RC:$src2, _.RC:$src3),
1773 (_.VT (X86VPermt2 _.RC:$src2, IdxVT.RC:$src1, _.RC:$src3)), 1>,
1895 (_.VT (X86VPermt2 _.RC:$src1, IdxVT.RC:$src2, _.RC:$src3)), 1>,
4105 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, _.RC:$src2)))],
4118 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
5425 _.RC:$src1, _.RC:$src2)>;
6767 (_.VT (OpNode _.RC:$src2, _.RC:$src1, _.RC:$src3)),
6768 (_.VT (MaskOpNode _.RC:$src2, _.RC:$src1, _.RC:$src3)), 1, 1>,
7384 (_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1)), 1, 1>,
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H A DX86InstrXOP.td332 (ins RC:$src1, RC:$src2, RC:$src3),
335 [(set RC:$dst, (VT (or (and RC:$src3, RC:$src1),
341 (ins RC:$src1, RC:$src2, x86memop:$src3),
347 (ins RC:$src1, x86memop:$src2, RC:$src3),
350 [(set RC:$dst, (VT (or (and RC:$src3, RC:$src1),
361 (ins RC:$src1, RC:$src2, RC:$src3),
421 (ins RC:$src1, RC:$src2, RC:$src3, u4imm:$src4),
425 (VT (X86vpermil2 RC:$src1, RC:$src2, RC:$src3, (i8 timm:$src4))))]>,
428 (ins RC:$src1, RC:$src2, intmemop:$src3, u4imm:$src4),
436 (ins RC:$src1, fpmemop:$src2, RC:$src3, u4imm:$src4),
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/llvm-project-15.0.7/llvm/utils/TableGen/
H A DRegisterBankEmitter.cpp73 if (llvm::is_contained(RCs, RC)) in addRegisterClass()
83 RCWithLargestRegsSize = RC; in addRegisterClass()
86 RCWithLargestRegsSize = RC; in addRegisterClass()
89 RCs.emplace_back(RC); in addRegisterClass()
175 if (!VisitedRCs.insert(RC).second) in visitRegisterBankClasses()
179 VisitFn(RC, Kind.str()); in visitRegisterBankClasses()
186 if (RC != &PossibleSubclass && RC->hasSubClass(&PossibleSubclass)) in visitRegisterBankClasses()
200 if (BV.test(RC->EnumValue)) { in visitRegisterBankClasses()
222 RCsGroupedByWord[RC->EnumValue / 32].push_back(RC); in emitBaseClassImplementation()
228 for (const auto &RC : RCs) { in emitBaseClassImplementation() local
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H A DRegisterInfoEmitter.cpp146 for (const auto &RC : RegisterClasses) in runEnums() local
220 if (Regs.empty() || RC.Artificial) in EmitRegUnitPressure()
1090 if (RC.RSI.isSimple()) in runMCDesc()
1093 << RegClassStrings.get(RC.getName()) << ", " << RC.getOrder().size() in runMCDesc()
1244 if (RC.Allocatable) in runTargetDesc()
1309 << RC.getName() << '\n'; in runTargetDesc()
1386 if (!RC.AltOrderSelect.empty()) { in runTargetDesc()
1406 if (RC.getOrder(oi).empty()) in runTargetDesc()
1426 printMask(OS, RC.LaneMask); in runTargetDesc()
1433 if (RC.getSuperClasses().empty()) in runTargetDesc()
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H A DCodeGenRegisters.cpp980 RC.SubClasses.set(RC.EnumValue); in computeSubClasses()
1009 if (&*I == &RC) in computeSubClasses()
1180 getReg(RC); in CodeGenRegBank()
1327 return RC; in getRegClass()
1943 if (!RC.Allocatable || RC.Artificial || !RC.GeneratePressureSet) in computeRegUnitSets()
2264 RC->setSubClassWithSubReg(&SubIdx, RC); in inferSubClassWithSubReg()
2293 if (RC->getSubClassWithSubReg(&SubIdx) != RC) in inferMatchingSuperRegClass()
2337 getOrCreateSubClass(RC, &SubSetVec, RC->getName() + "_with_" + in inferMatchingSuperRegClass()
2405 FoundRC = &RC; in getRegClassForRegister()
2441 RC.contains(Reg) && (!BestRC || BestRC->hasSubClass(&RC))) in getMinimalPhysRegClass()
[all …]
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DRegisterClassInfo.h76 void compute(const TargetRegisterClass *RC) const;
79 const RCInfo &get(const TargetRegisterClass *RC) const { in get() argument
80 const RCInfo &RCI = RegClass[RC->getID()]; in get()
82 compute(RC); in get()
96 return get(RC).NumRegs; in getNumAllocatableRegs()
103 return get(RC); in getOrder()
112 bool isProperSubClass(const TargetRegisterClass *RC) const { in isProperSubClass() argument
113 return get(RC).ProperSubClass; in isProperSubClass()
128 uint8_t getMinCost(const TargetRegisterClass *RC) const { in getMinCost() argument
129 return get(RC).MinCost; in getMinCost()
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H A DTargetRegisterInfo.h123 return RC != this && hasSubClassEq(RC); in hasSubClass()
128 unsigned ID = RC->getID(); in hasSubClassEq()
135 return RC->hasSubClass(this); in hasSuperClass()
140 return RC->hasSubClassEq(this); in hasSuperClassEq()
278 return getRegClassInfo(RC).RegSize; in getRegSizeInBits()
284 return getRegClassInfo(RC).SpillSize / 8; in getSpillSize()
317 return getRegClassInfo(RC).VTList; in legalclasstypes_begin()
626 return RC; in getSubClassWithSubReg()
780 return RC; in getCrossCopyRegClass()
792 return RC; in getLargestLegalSuperClass()
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/llvm-project-15.0.7/llvm/unittests/Analysis/
H A DLazyCallGraphTest.cpp479 auto J = RC.begin(); in TEST()
1298 J = RC.begin(); in TEST()
1483 EXPECT_EQ(RC.end(), std::next(RC.begin())); in TEST()
1605 J = RC.find(AC); in TEST()
2293 EXPECT_EQ(RC, ORC); in TEST()
2338 EXPECT_EQ(RC, ORC); in TEST()
2384 EXPECT_EQ(RC, ORC); in TEST()
2428 EXPECT_EQ(RC, ORC); in TEST()
2479 EXPECT_EQ(RC, ORC); in TEST()
2532 EXPECT_EQ(RC, ORC); in TEST()
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/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DRegisterClassInfo.cpp106 assert(RC && "no register class given"); in compute()
107 RCInfo &RCI = RegClass[RC->getID()]; in compute()
111 unsigned NumRegs = RC->getNumRegs(); in compute()
162 TRI->getLargestLegalSuperClass(RC, *MF)) in compute()
184 const TargetRegisterClass *RC = nullptr; in computePSetLimit() local
198 if (!RC || NUnits > NumRCUnits) { in computePSetLimit()
199 RC = C; in computePSetLimit()
203 assert(RC && "Failed to find register class"); in computePSetLimit()
204 compute(RC); in computePSetLimit()
205 unsigned NAllocatableRegs = getNumAllocatableRegs(RC); in computePSetLimit()
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H A DTargetRegisterInfo.cpp196 if (!RC || RC->isAllocatable()) in getAllocatableClass()
197 return RC; in getAllocatableClass()
221 RC->contains(reg) && (!BestRC || BestRC->hasSubClass(RC))) in getMinimalPhysRegClass()
222 BestRC = RC; in getMinimalPhysRegClass()
238 if ((!Ty.isValid() || isTypeLegalForClass(*RC, Ty)) && RC->contains(reg) && in getMinimalPhysRegClassLLT()
240 BestRC = RC; in getMinimalPhysRegClassLLT()
259 if (RC) { in getAllocatableSet()
355 if (!RC || getRegSizeInBits(*RC) < MinSize) in getCommonSuperRegClass()
368 BestRC = RC; in getCommonSuperRegClass()
518 RC = MRI.getRegClass(Reg); in getRegSizeInBits()
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H A DRegisterBank.cpp35 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); in verify() local
37 if (!covers(RC)) in verify()
48 if (!RC.hasSubClassEq(&SubRC)) in verify()
61 bool RegisterBank::covers(const TargetRegisterClass &RC) const { in covers()
63 return ContainedRegClasses.test(RC.getID()); in covers()
105 const TargetRegisterClass &RC = *TRI->getRegClass(RCId); in print() local
107 if (covers(RC)) in print()
108 OS << LS << TRI->getRegClassName(&RC); in print()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsCondMov.td37 InstSE<(outs RC:$rd), (ins RC:$rs, FCCRegsOpnd:$fcc, RC:$F),
39 [(set RC:$rd, (OpNode RC:$rs, FCCRegsOpnd:$fcc, RC:$F))],
47 InstSE<(outs RC:$fd), (ins RC:$fs, FCCRegsOpnd:$fcc, RC:$F),
49 [(set RC:$fd, (OpNode RC:$fs, FCCRegsOpnd:$fcc, RC:$F))],
268 PseudoSE<(outs RC:$dst), (ins GPR32Opnd:$cond, RC:$T, RC:$F),
269 [(set RC:$dst, (select GPR32Opnd:$cond, RC:$T, RC:$F))]>,
273 PseudoSE<(outs RC:$dst), (ins FCCRegsOpnd:$cond, RC:$T, RC:$F),
274 [(set RC:$dst, (MipsCMovFP_T RC:$T, FCCRegsOpnd:$cond, RC:$F))]>,
278 PseudoSE<(outs RC:$dst), (ins FCCRegsOpnd:$cond, RC:$T, RC:$F),
303 PseudoSE<(outs RC:$dst1, RC:$dst2),
[all …]
H A DMipsInstrFPU.td113 InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft),
115 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR, opstr>,
204 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
206 [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))], Itin,
211 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
213 [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))],
260 InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond),
986 def : MipsPat<(fneg (fadd (fmul RC:$fs, RC:$ft), RC:$fr)),
987 (Nmadd RC:$fr, RC:$fs, RC:$ft)>;
988 def : MipsPat<(fneg (fsub (fmul RC:$fs, RC:$ft), RC:$fr)),
[all …]
H A DMipsMachineFunction.cpp78 const TargetRegisterClass *RC; in initGlobalBaseReg() local
81 RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in initGlobalBaseReg()
83 Register V0 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
84 Register V1 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
159 const TargetRegisterClass &RC = in createEhDataRegsFI() local
164 I = MF.getFrameInfo().CreateStackObject(TRI.getSpillSize(RC), in createEhDataRegsFI()
165 TRI.getSpillAlign(RC), false); in createEhDataRegsFI()
174 const TargetRegisterClass &RC = Mips::GPR32RegClass; in createISRRegFI() local
178 I = MF.getFrameInfo().CreateStackObject(TRI.getSpillSize(RC), in createISRRegFI()
179 TRI.getSpillAlign(RC), false); in createISRRegFI()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/XCore/
H A DXCoreMachineFunctionInfo.cpp45 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createLRSpillSlot() local
50 LRSpillSlot = MFI.CreateFixedObject(TRI.getSpillSize(RC), 0, true); in createLRSpillSlot()
52 LRSpillSlot = MFI.CreateStackObject(TRI.getSpillSize(RC), in createLRSpillSlot()
53 TRI.getSpillAlign(RC), true); in createLRSpillSlot()
63 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createFPSpillSlot() local
67 MFI.CreateStackObject(TRI.getSpillSize(RC), TRI.getSpillAlign(RC), true); in createFPSpillSlot()
76 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createEHSpillSlot() local
79 unsigned Size = TRI.getSpillSize(RC); in createEHSpillSlot()
80 Align Alignment = TRI.getSpillAlign(RC); in createEHSpillSlot()
/llvm-project-15.0.7/llvm/utils/release/
H A Dtest-release.sh24 RC=""
89 -rc | --rc | -RC | --RC )
91 RC="rc$1"
94 RC=final
210 if [ -z "$RC" ]; then
228 if [ "$RC" != "final" ]; then
229 git_ref="$git_ref-$RC"
285 BuildDir=$BuildDir/$RC
295 if [ $RC != "final" ]; then
296 Package=$Package-$RC
[all …]
/llvm-project-15.0.7/llvm/lib/Analysis/
H A DCGSCCPassManager.cpp192 RCWorklist.insert(&RC); in run()
630 for (auto &C : RC) { in invalidate()
901 RefSCC *RC = &InitialRC; in updateCGAndAnalysisManagerForPass() local
982 assert((RC == &TargetRC || in updateCGAndAnalysisManagerForPass()
995 assert((RC == &TargetRC || in updateCGAndAnalysisManagerForPass()
1041 if (&TargetRC == RC) in updateCGAndAnalysisManagerForPass()
1063 RC = &C->getOuterRefSCC(); in updateCGAndAnalysisManagerForPass()
1089 if (&TargetRC != RC) { in updateCGAndAnalysisManagerForPass()
1125 if (&TargetRC != RC) { in updateCGAndAnalysisManagerForPass()
1143 auto InitialSCCIndex = RC->find(*C) - RC->begin(); in updateCGAndAnalysisManagerForPass()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEInstrVec.td136 def _v : RVM<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)),
241 def _v : RVM<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)),
378 def _v : RR<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)),
449 def _v : RV<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)),
587 defm vv : RVmm<opcStr, ", $vy, $vz", opc, RC, RCM, (ins RC:$vy, RC:$vz)>;
599 defm v : RVmm<opcStr, ", $vz", opc, RC, RCM, (ins RC:$vz)>;
615 defm vv : RVmm<opcStr, ", $vz, $vy", opc, RC, RCM, (ins RC:$vz, RC:$vy)>;
628 (ins RC:$vy, RC:$vz, I64:$sy)>;
631 (ins RC:$vy, RC:$vz, uimm7:$sy)>;
657 defm v : RVmm<opcStr, ", $vy", opc, RC, RCM, (ins RC:$vy)>;
[all …]
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DConstantFolder.h46 auto *RC = dyn_cast<Constant>(RHS); in FoldBinOp() local
47 if (LC && RC) { in FoldBinOp()
49 return ConstantExpr::get(Opc, LC, RC); in FoldBinOp()
58 auto *RC = dyn_cast<Constant>(RHS); in FoldExactBinOp() local
59 if (LC && RC) { in FoldExactBinOp()
61 return ConstantExpr::get(Opc, LC, RC, in FoldExactBinOp()
71 auto *RC = dyn_cast<Constant>(RHS); in FoldNoWrapBinOp() local
72 if (LC && RC) { in FoldNoWrapBinOp()
100 auto *RC = dyn_cast<Constant>(RHS); in FoldICmp() local
101 if (LC && RC) in FoldICmp()
[all …]

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