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Searched refs:EXTRACT_VECTOR_ELT (Results 1 – 25 of 44) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp144 setOperationAction(ISD::EXTRACT_VECTOR_ELT, in R600TargetLowering()
399 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); in LowerOperation()
492 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
494 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
496 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
498 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
645 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, Op.getValueType(), in LowerEXTRACT_VECTOR_ELT()
1601 if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in ReorganizeVector()
1610 if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in ReorganizeVector()
1686 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result, in constBufferLoad()
[all …]
H A DSIISelLowering.cpp253 case ISD::EXTRACT_VECTOR_ELT: in SITargetLowering()
521 case ISD::EXTRACT_VECTOR_ELT: in SITargetLowering()
745 ISD::EXTRACT_VECTOR_ELT, in SITargetLowering()
4678 case ISD::EXTRACT_VECTOR_ELT: in LowerOperation()
4980 case ISD::EXTRACT_VECTOR_ELT: { in ReplaceNodeResults()
10104 case ISD::EXTRACT_VECTOR_ELT: in isCanonicalized()
11220 if (Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in performFMACombine()
11221 Op2.getOpcode() != ISD::EXTRACT_VECTOR_ELT) in performFMACombine()
11238 if (FMAOp1.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in performFMACombine()
11239 FMAOp2.getOpcode() != ISD::EXTRACT_VECTOR_ELT) in performFMACombine()
[all …]
H A DAMDGPUISelDAGToDAG.cpp54 if (In.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in isExtractHiElt()
82 if (In.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in stripExtractLoElt()
749 if (BaseLo.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in getBaseWithOffsetUsingSplitOR()
750 BaseHi.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in getBaseWithOffsetUsingSplitOR()
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A DDAGCombine_trunc_extract.ll4 ; when handling EXTRACT_VECTOR_ELT without vector support.
H A Ddag-combine-03.ll7 ; The EXTRACT_VECTOR_ELT is done first into an i32, and then AND:ed with
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp243 Oper = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, in ScalarizeVecRes_StrictFPOp()
326 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), in ScalarizeVecRes_EXTRACT_SUBVECTOR()
341 Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Op, in ScalarizeVecRes_FP_ROUND()
399 Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Op, in ScalarizeVecRes_UnaryOp()
424 Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, OpEltVT, Op, in ScalarizeVecRes_VecInregOp()
461 Cond = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Cond, in ScalarizeVecRes_VSELECT()
579 LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, LHS, in ScalarizeVecRes_SETCC()
581 RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, RHS, in ScalarizeVecRes_SETCC()
606 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Arg, in ScalarizeVecRes_IS_FPCLASS()
659 case ISD::EXTRACT_VECTOR_ELT: in ScalarizeVectorOperand()
[all …]
H A DLegalizeTypesGeneric.cpp125 Vals.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ElemVT, in ExpandRes_BITCAST()
239 Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); in ExpandRes_EXTRACT_VECTOR_ELT()
243 Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); in ExpandRes_EXTRACT_VECTOR_ELT()
H A DLegalizeFloatTypes.cpp69 case ISD::EXTRACT_VECTOR_ELT: in SoftenFloatResult()
258 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), in SoftenFloatRes_EXTRACT_VECTOR_ELT()
1211 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break; in ExpandFloatResult()
2251 case ISD::EXTRACT_VECTOR_ELT: in PromoteFloatResult()
2405 SDValue NewVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, IVT, in PromoteFloatRes_EXTRACT_VECTOR_ELT()
2613 case ISD::EXTRACT_VECTOR_ELT: in SoftPromoteHalfResult()
2695 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), in SoftPromoteHalfRes_EXTRACT_VECTOR_ELT()
H A DLegalizeDAG.cpp1004 case ISD::EXTRACT_VECTOR_ELT: in LegalizeOp()
3009 case ISD::EXTRACT_VECTOR_ELT: in ExpandNode()
3095 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0, in ExpandNode()
3099 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op1, in ExpandNode()
3812 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT.getScalarType(), in ExpandNode()
3815 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT.getScalarType(), in ExpandNode()
4453 Node->getOpcode() == ISD::EXTRACT_VECTOR_ELT || in PromoteNode()
4908 case ISD::EXTRACT_VECTOR_ELT: { in PromoteNode()
4943 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, NewEltVT, in PromoteNode()
4992 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, NewEltVT, in PromoteNode()
H A DLegalizeVectorOps.cpp1601 Oper = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, in UnrollStrictFPOp()
1639 SDValue LHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS, in UnrollVSETCC()
1641 SDValue RHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS, in UnrollVSETCC()
H A DDAGCombiner.cpp658 case ISD::EXTRACT_VECTOR_ELT: in getStoreSource()
6257 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitAND()
13232 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitTRUNCATE()
17964 (Val.getOpcode() == ISD::EXTRACT_VECTOR_ELT || in mergeStoresOfConstantsOrVecElts()
19370 InsertVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in combineInsertEltToShuffle()
19513 if (InVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitINSERT_VECTOR_ELT()
19544 if (InVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitINSERT_VECTOR_ELT()
20051 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, in visitEXTRACT_VECTOR_ELT()
20518 if (Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in reduceBuildVecToShuffle()
20819 if ((Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT) && in visitBUILD_VECTOR()
[all …]
H A DLegalizeIntegerTypes.cpp72 case ISD::EXTRACT_VECTOR_ELT: in PromoteIntegerResult()
649 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, In, Op1); in PromoteIntRes_EXTRACT_VECTOR_ELT()
654 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, Op0, Op1); in PromoteIntRes_EXTRACT_VECTOR_ELT()
1637 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break; in PromoteIntegerOperand()
2407 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break; in ExpandIntegerResult()
5245 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, in PromoteIntRes_EXTRACT_SUBVECTOR()
5424 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SclrTy, Op, in PromoteIntRes_CONCAT_VECTORS()
5507 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, in PromoteIntOp_EXTRACT_VECTOR_ELT()
5573 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SclrTy, Incoming, in PromoteIntOp_CONCAT_VECTORS()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h534 EXTRACT_VECTOR_ELT, enumerator
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp203 for (auto Op : {ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT}) in WebAssemblyTargetLowering()
1412 case ISD::EXTRACT_VECTOR_ELT: in LowerOperation()
1944 if (Op.getOperand(0).getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerSIGN_EXTEND_INREG()
1969 ISD::EXTRACT_VECTOR_ELT, DL, Extract.getValueType(), in LowerSIGN_EXTEND_INREG()
1997 if (ExtractVector.getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerConvertLow()
2072 if (Lane->getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerBUILD_VECTOR()
2079 if (Index->getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerBUILD_VECTOR()
2095 if (Lane->getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerBUILD_VECTOR()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp363 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Legal); in SystemZTargetLowering()
652 ISD::EXTRACT_VECTOR_ELT, in SystemZTargetLowering()
5241 if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in tryBuildVectorShuffle()
5797 case ISD::EXTRACT_VECTOR_ELT: in LowerOperation()
6148 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResVT, Op, in combineExtract()
6161 if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in combineTruncateExtract()
6581 Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), EltVT, in combineEXTRACT_VECTOR_ELT()
6642 Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in combineFP_ROUND()
6650 U->getOpcode() == ISD::EXTRACT_VECTOR_ELT && in combineFP_ROUND()
6708 Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in combineFP_EXTEND()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp407 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f16, Custom); in NVPTXTargetLowering()
1940 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp, in LowerCONCAT_VECTORS()
1988 SDValue E0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Vector, in LowerEXTRACT_VECTOR_ELT()
1990 SDValue E1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Vector, in LowerEXTRACT_VECTOR_ELT()
2226 case ISD::EXTRACT_VECTOR_ELT: in LowerOperation()
2414 SDValue E0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f16, Val, in LowerSTOREVector()
2416 SDValue E1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f16, Val, in LowerSTOREVector()
2424 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Val, in LowerSTOREVector()
2602 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, LoadVT, P, in LowerFormalArguments()
5027 SDValue E0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, SubVector, in ReplaceLoadVector()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp171 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); in addTypeForNEON()
253 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); in addMVEVectorTypes()
333 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); in addMVEVectorTypes()
1014 ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT, in ARMTargetLowering()
8674 ISD::EXTRACT_VECTOR_ELT, dl, SVT, in LowerVECTOR_SHUFFLEUsingOneOff()
14990 if (N0->getOpcode() == ISD::EXTRACT_VECTOR_ELT && in PerformVMOVrhCombine()
15270 if (Ext.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in PerformExtractEltToVMOVRRD()
15288 return V->getOpcode() == ISD::EXTRACT_VECTOR_ELT && in PerformExtractEltToVMOVRRD()
15309 ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, in PerformExtractEltToVMOVRRD()
17576 N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in PerformExtendCombine()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp2328 ISD::EXTRACT_VECTOR_ELT, in X86TargetLowering()
9174 case ISD::EXTRACT_VECTOR_ELT: in findEltLoadSrc()
9850 if (Opc != ISD::EXTRACT_VECTOR_ELT) { in buildFromShuffleMostly()
11006 if (Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerBUILD_VECTORAsVariablePermute()
23098 if (LHS.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in lowerAddSubToHorizontalOp()
23099 RHS.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in lowerAddSubToHorizontalOp()
23412 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT) in matchScalarReduction()
23579 if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in MatchVectorAllZeroTest()
48041 N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in combineAnd()
51759 if (V.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in combineFMA()
[all …]
/llvm-project-15.0.7/llvm/utils/
H A Dupdate_mir_test_checks.py275 EXTRACT_VECTOR_ELT='EVEC',
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp201 setOperationAction(ISD::EXTRACT_VECTOR_ELT, T, Custom); in initializeHVXLowering()
348 setOperationAction(ISD::EXTRACT_VECTOR_ELT, BoolV, Custom); in initializeHVXLowering()
695 if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) in buildHvxVectorReg()
1490 if (V.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in LowerHvxConcatVectors()
1492 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NTy, in LowerHvxConcatVectors()
1879 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i8, ValAsVec, Idx); in LowerHvxBitcast()
2450 case ISD::EXTRACT_VECTOR_ELT: return LowerHvxExtractElement(Op, DAG); in LowerHvxOperation()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp5456 case ISD::EXTRACT_VECTOR_ELT: in LowerOperation()
11205 if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerBUILD_VECTOR()
15045 assert(N->getOpcode() == ISD::EXTRACT_VECTOR_ELT); in performFirstTrueTestVectorCombine()
15075 assert(N->getOpcode() == ISD::EXTRACT_VECTOR_ELT); in performLastTrueTestVectorCombine()
15108 assert(N->getOpcode() == ISD::EXTRACT_VECTOR_ELT); in performExtractVectorEltCombine()
15427 if (Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT) in tryCombineFixedPointConvert()
15668 if (LHS.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in performAddUADDVCombine()
15691 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, in performAddUADDVCombine()
16009 if (Elt0->getOpcode() == ISD::EXTRACT_VECTOR_ELT && in performBuildVectorCombine()
19620 case ISD::EXTRACT_VECTOR_ELT: in PerformDAGCombine()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCTargetTransformInfo.cpp1089 if (ISD == ISD::EXTRACT_VECTOR_ELT && in getVectorInstrCost()
1137 if (ISD == ISD::EXTRACT_VECTOR_ELT || in getVectorInstrCost()
H A DREADME_ALTIVEC.txt314 Currently EXTRACT_VECTOR_ELT and INSERT_VECTOR_ELT are type-legal only
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp473 setOperationAction({ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT}, in RISCVTargetLowering()
767 setOperationAction({ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT}, in RISCVTargetLowering()
886 ISD::EXTRACT_VECTOR_ELT}, in RISCVTargetLowering()
2036 if (SplatVal.getOpcode() != ISD::EXTRACT_VECTOR_ELT) in matchSplatAsGather()
3179 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, BVec, in LowerOperation()
3258 case ISD::EXTRACT_VECTOR_ELT: in LowerOperation()
4620 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Vec, Idx); in lowerEXTRACT_VECTOR_ELT()
4641 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Vec, in lowerEXTRACT_VECTOR_ELT()
5329 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VecEltVT, Reduction, in lowerFPVECREDUCE()
7209 case ISD::EXTRACT_VECTOR_ELT: { in ReplaceNodeResults()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEISelLowering.cpp308 setOperationAction(ISD::EXTRACT_VECTOR_ELT, LegalVecVT, Legal); in initVPUActions()
325 setOperationAction(ISD::EXTRACT_VECTOR_ELT, LegalPackedVT, Custom); in initVPUActions()
1906 case ISD::EXTRACT_VECTOR_ELT: in LowerOperation()
2881 assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!"); in lowerEXTRACT_VECTOR_ELT()

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