171   setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);  in addTypeForNEON()
253     setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);  in addMVEVectorTypes()
333     setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);  in addMVEVectorTypes()
396     setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);  in addMVEVectorTypes()
445     setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);  in addMVEVectorTypes()
1014          ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,  in ARMTargetLowering()
2512       SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,  in LowerCall()
2514       SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,  in LowerCall()
3234         SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,  in LowerReturn()
3253         Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,  in LowerReturn()
6027       Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,  in LowerFCOPYSIGN()
6155   if (!DstVT.isVector() || Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||  in CombineVMOVDRRCandidateWithVecOp()
7096     return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecConstant,  in LowerConstantFP()
7127     return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,  in LowerConstantFP()
7144     return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,  in LowerConstantFP()
7557       BV.getOperand(0).getOperand(0).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||  in LowerBuildVectorOfFPTrunc()
7561       BV.getOperand(1).getOperand(0).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||  in LowerBuildVectorOfFPTrunc()
7573              Trunc.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&  in LowerBuildVectorOfFPTrunc()
7610       BV.getOperand(0).getOperand(0).getOpcode() != ISD::EXTRACT_VECTOR_ELT)  in LowerBuildVectorOfFPExt()
7621              Trunc.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&  in LowerBuildVectorOfFPExt()
7932       if (Value->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&  in LowerBUILD_VECTOR()
8097     else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {  in ReconstructShuffle()
8598       Parts[Part] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, BitCast,  in LowerVECTOR_SHUFFLEUsingMovs()
8621         Parts[Part] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32,  in LowerVECTOR_SHUFFLEUsingMovs()
8674       ISD::EXTRACT_VECTOR_ELT, dl, SVT,  in LowerVECTOR_SHUFFLEUsingOneOff()
8866         Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,  in LowerVECTOR_SHUFFLE()
9028         SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, NewV,  in LowerCONCAT_VECTORS_i1()
9116       SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, NewV1,  in LowerEXTRACT_SUBVECTOR()
9131     SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, NewV1,  in LowerEXTRACT_SUBVECTOR()
10048       Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, Build,  in LowerPredicateStore()
10172     SDValue Ext0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0,  in LowerVecReduce()
10174     SDValue Ext1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0,  in LowerVecReduce()
10176     SDValue Ext2 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0,  in LowerVecReduce()
10178     SDValue Ext3 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0,  in LowerVecReduce()
10184     SDValue Ext0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0,  in LowerVecReduce()
10186     SDValue Ext1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0,  in LowerVecReduce()
10390   case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG, Subtarget);  in LowerOperation()
12505   if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT)  in AddCombineBUILD_VECTORToVPADDL()
12515     if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT  in AddCombineBUILD_VECTORToVPADDL()
12516         && N1->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {  in AddCombineBUILD_VECTORToVPADDL()
14853   if (InDouble.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&  in PerformVMOVRRDCombine()
14990   if (N0->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&  in PerformVMOVrhCombine()
15270   if (Ext.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||  in PerformExtractEltToVMOVRRD()
15288     return V->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&  in PerformExtractEltToVMOVRRD()
15309       ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,  in PerformExtractEltToVMOVRRD()
15373     return DCI.DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Op0.getOperand(Vec),  in PerformExtractEltCombine()
16262     SDValue Extract = DCI.DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), ExtractVT,  in PerformVDUPLANECombine()
16417     SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, StoreType,  in PerformTruncatingStoreCombine()
16574   if (VT != MVT::f16 || Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)  in PerformExtractFpToIntStores()
16650       StVal.getNode()->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {  in PerformSTORECombine()
16660     SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,  in PerformSTORECombine()
17576       N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {  in PerformExtendCombine()
18367         SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, O,  in PerformMVETruncCombine()
18611   case ISD::EXTRACT_VECTOR_ELT:  in PerformDAGCombine()