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Searched refs:EXTLOAD (Results 1 – 25 of 45) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp153 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand); in AMDGPUTargetLowering()
154 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, MVT::v2f16, Expand); in AMDGPUTargetLowering()
155 setLoadExtAction(ISD::EXTLOAD, MVT::v3f32, MVT::v3f16, Expand); in AMDGPUTargetLowering()
156 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Expand); in AMDGPUTargetLowering()
157 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, MVT::v8f16, Expand); in AMDGPUTargetLowering()
161 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand); in AMDGPUTargetLowering()
162 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f32, Expand); in AMDGPUTargetLowering()
163 setLoadExtAction(ISD::EXTLOAD, MVT::v3f64, MVT::v3f32, Expand); in AMDGPUTargetLowering()
164 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Expand); in AMDGPUTargetLowering()
165 setLoadExtAction(ISD::EXTLOAD, MVT::v8f64, MVT::v8f32, Expand); in AMDGPUTargetLowering()
[all …]
H A DR600ISelLowering.cpp49 for (auto Op : {ISD::SEXTLOAD, ISD::ZEXTLOAD, ISD::EXTLOAD}) in R600TargetLowering()
57 setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, MVT::v2i32, in R600TargetLowering()
60 setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, MVT::v4i32, in R600TargetLowering()
1364 ISD::EXTLOAD, DL, VT, Chain, Ptr, LoadNode->getPointerInfo(), MemVT, in LowerLOAD()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp706 case ISD::EXTLOAD: OS << ", anyext"; break; in print_details()
738 case ISD::EXTLOAD: OS << ", anyext"; break; in print_details()
775 case ISD::EXTLOAD: OS << ", anyext"; break; in print_details()
H A DLegalizeDAG.cpp316 TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) && in ExpandConstantFP()
331 ISD::EXTLOAD, dl, OrigVT, DAG.getEntryNode(), CPIdx, in ExpandConstantFP()
749 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; in LegalizeLoadOps()
877 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, DestVT, SrcVT)) { in LegalizeLoadOps()
921 assert(ExtType != ISD::EXTLOAD && in LegalizeLoadOps()
925 SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl, in LegalizeLoadOps()
1419 NewLoad = DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr, in ExpandExtractFromVectorThroughStack()
1572 State.IntValue = DAG.getExtLoad(ISD::EXTLOAD, DL, LoadTy, State.Chain, IntPtr, in getSignAsIntValue()
1747 !TLI.isLoadExtLegalOrCustom(ISD::EXTLOAD, DestVT, SlotVT))) in EmitStackConvert()
1777 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, PtrInfo, SlotVT, in EmitStackConvert()
[all …]
H A DDAGCombiner.cpp1279 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) ? ISD::EXTLOAD in PromoteOperand()
1516 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) ? ISD::EXTLOAD in PromoteLoad()
6322 case ISD::EXTLOAD: B = CanZextLoadProfitably; break; in visitAND()
6335 if (Load->getExtensionType() == ISD::EXTLOAD) { in visitAND()
11257 if (LoadExt == ISD::NON_EXTLOAD || LoadExt == ISD::EXTLOAD) in isCompatibleLoad()
11295 auto ExtLoadOpcode = ISD::EXTLOAD; in tryToFoldExtendSelectLoad()
15838 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(N), VT, in visitFP_EXTEND()
16638 case ISD::EXTLOAD: in extendLoadedValueToExtension()
18770 NewLoad = DAG.getExtLoad(ISD::EXTLOAD, LoadDL, ExtendedTy, in tryStoreMergeOfLoads()
23759 LLD->getExtensionType() != ISD::EXTLOAD && in SimplifySelectOps()
[all …]
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1404 enum LoadExtType { NON_EXTLOAD = 0, EXTLOAD, SEXTLOAD, ZEXTLOAD }; enumerator
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp47 setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, GRLenVT, in LoongArchTargetLowering()
78 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand); in LoongArchTargetLowering()
79 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand); in LoongArchTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp137 setLoadExtAction(ISD::EXTLOAD, T, MVT::f16, Expand); in WebAssemblyTargetLowering()
292 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand); in WebAssemblyTargetLowering()
295 for (auto Ext : {ISD::EXTLOAD, ISD::ZEXTLOAD, ISD::SEXTLOAD}) in WebAssemblyTargetLowering()
303 for (auto Ext : {ISD::EXTLOAD, ISD::ZEXTLOAD, ISD::SEXTLOAD}) in WebAssemblyTargetLowering()
309 for (auto Ext : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) { in WebAssemblyTargetLowering()
314 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f32, Legal); in WebAssemblyTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp468 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand); in NVPTXTargetLowering()
469 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand); in NVPTXTargetLowering()
470 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand); in NVPTXTargetLowering()
471 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, MVT::v2f16, Expand); in NVPTXTargetLowering()
472 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Expand); in NVPTXTargetLowering()
473 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f32, Expand); in NVPTXTargetLowering()
474 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Expand); in NVPTXTargetLowering()
475 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f16, Expand); in NVPTXTargetLowering()
476 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Expand); in NVPTXTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp124 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in XCoreTargetLowering()
450 DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain, HighAddr, in LowerLOAD()
952 return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), MVT::i32, N->getChain(), in LowerATOMIC_LOAD()
958 return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), MVT::i32, N->getChain(), in LowerATOMIC_LOAD()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1600 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand); in HexagonTargetLowering()
1606 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); in HexagonTargetLowering()
1658 setLoadExtAction(ISD::EXTLOAD, TargetVT, VT, Expand); in HexagonTargetLowering()
1677 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, MVT::v2i8, Legal); in HexagonTargetLowering()
1680 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, MVT::v4i8, Legal); in HexagonTargetLowering()
1781 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand); in HexagonTargetLowering()
1782 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand); in HexagonTargetLowering()
H A DHexagonISelDAGToDAG.cpp77 bool IsZeroExt = (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD); in SelectIndexedLoad()
133 if (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD) { in SelectIndexedLoad()
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kInstrInfo.td524 if (ExtType == ISD::EXTLOAD)
534 if (ExtType == ISD::EXTLOAD)
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYISelLowering.cpp82 setLoadExtAction(ISD::EXTLOAD, MVT::i32, MVT::i1, Promote); in CSKYTargetLowering()
138 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand); in CSKYTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZOperators.td516 return Type == ISD::EXTLOAD || Type == ISD::SEXTLOAD;
531 return Type == ISD::EXTLOAD || Type == ISD::ZEXTLOAD;
H A DSystemZISelLowering.cpp306 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in SystemZTargetLowering()
338 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand); in SystemZTargetLowering()
619 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f80, Expand); in SystemZTargetLowering()
623 setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f32, Expand); in SystemZTargetLowering()
624 setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f64, Expand); in SystemZTargetLowering()
4158 return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), Op.getValueType(), in lowerATOMIC_LOAD()
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1539 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Expand); in SparcTargetLowering()
1543 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, VT, Expand); in SparcTargetLowering()
1565 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand); in SparcTargetLowering()
1566 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); in SparcTargetLowering()
1567 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand); in SparcTargetLowering()
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td832 // cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
1719 return MGN->getExtensionType() == ISD::EXTLOAD &&
1726 return MGN->getExtensionType() == ISD::EXTLOAD &&
1733 return MGN->getExtensionType() == ISD::EXTLOAD &&
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp302 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in MipsTargetLowering()
310 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); in MipsTargetLowering()
311 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand); in MipsTargetLowering()
318 setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand); in MipsTargetLowering()
477 setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom); in MipsTargetLowering()
2723 (ExtType == ISD::EXTLOAD)) in lowerLOAD()
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp140 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in BPFTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp197 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Legal); in PPCTargetLowering()
198 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Legal); in PPCTargetLowering()
203 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand); in PPCTargetLowering()
206 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand); in PPCTargetLowering()
419 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand); in PPCTargetLowering()
867 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand); in PPCTargetLowering()
1157 setLoadExtAction(ISD::EXTLOAD, MVT::f128, FPT, Expand); in PPCTargetLowering()
13996 return LD->getExtensionType() == ISD::EXTLOAD && in isFPExtLoad()
14114 IsRoundOfExtLoad = LD->getExtensionType() == ISD::EXTLOAD; in combineBVOfConsecutiveLoads()
14346 LD->getExtensionType() != ISD::EXTLOAD)) in combineBVZEXTLOAD()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp822 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand); in AArch64TargetLowering()
823 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); in AArch64TargetLowering()
824 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand); in AArch64TargetLowering()
825 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f80, Expand); in AArch64TargetLowering()
1098 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand); in AArch64TargetLowering()
1259 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand); in AArch64TargetLowering()
1495 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand); in addTypeForNEON()
1624 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Custom); in addTypeForFixedLengthSVE()
4989 ExtType = ISD::EXTLOAD; in LowerMGATHER()
5300 LoadNode->getExtensionType() == ISD::EXTLOAD) in LowerLOAD()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp180 setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, XLenVT, in RISCVTargetLowering()
353 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand); in RISCVTargetLowering()
368 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand); in RISCVTargetLowering()
371 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand); in RISCVTargetLowering()
526 setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, OtherVT, in RISCVTargetLowering()
613 setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, OtherVT, in RISCVTargetLowering()
715 setLoadExtAction(ISD::EXTLOAD, VT, SmallVT, Expand); in RISCVTargetLowering()
756 setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, in RISCVTargetLowering()
876 setLoadExtAction(ISD::EXTLOAD, OtherVT, VT, Expand); in RISCVTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEISelLowering.cpp107 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in initSPUActions()
114 setLoadExtAction(ISD::EXTLOAD, FPVT, OtherFPVT, Expand); in initSPUActions()
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp136 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in LanaiTargetLowering()

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