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Searched refs:DestVT (Results 1 – 22 of 22) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp1203 MVT DestVT = VA.getLocVT(); in processCallArgs() local
1211 MVT DestVT = VA.getLocVT(); in processCallArgs() local
1744 MVT DestVT = VA.getValVT(); in selectRet() local
1746 if (RVVT != DestVT) { in selectRet()
1776 EVT SrcVT, DestVT; in selectTrunc() local
1782 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1) in selectTrunc()
1814 MVT DestVT = DestEVT.getSimpleVT(); in selectIntExt() local
1859 if ((DestVT != MVT::i32) && (DestVT != MVT::i16)) in emitIntSExt()
1894 if (((DestVT != MVT::i8) && (DestVT != MVT::i16) && (DestVT != MVT::i32)) || in emitIntExt()
1914 MVT DestVT = DestEVT.getSimpleVT(); in selectDivRem() local
[all …]
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp1274 if (DestVT != MVT::i16 && DestVT != MVT::i8) in SelectBinaryIntOp()
1442 MVT DestVT = VA.getLocVT(); in processCallArgs() local
1448 ArgVT = DestVT; in processCallArgs()
1454 MVT DestVT = VA.getLocVT(); in processCallArgs() local
1460 ArgVT = DestVT; in processCallArgs()
1509 MVT DestVT = VA.getValVT(); in finishCall() local
1510 MVT CopyVT = DestVT; in finishCall()
1761 if (RVVT != DestVT) { in SelectRet()
1810 if (DestVT != MVT::i32 && DestVT != MVT::i64) in PPCEmitIntExt()
1830 } else if (DestVT == MVT::i32) { in PPCEmitIntExt()
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H A DPPCISelLowering.h1024 bool isFPExtFree(EVT DestVT, EVT SrcVT) const override;
H A DPPCISelLowering.cpp8964 if (DestVT == MVT::Other) DestVT = Op.getValueType(); in BuildIntrinsicOp()
8965 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, in BuildIntrinsicOp()
8973 EVT DestVT = MVT::Other) { in BuildIntrinsicOp() argument
8974 if (DestVT == MVT::Other) DestVT = LHS.getValueType(); in BuildIntrinsicOp()
8975 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, in BuildIntrinsicOp()
8983 EVT DestVT = MVT::Other) { in BuildIntrinsicOp() argument
8984 if (DestVT == MVT::Other) DestVT = Op0.getValueType(); in BuildIntrinsicOp()
8985 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, in BuildIntrinsicOp()
16639 bool PPCTargetLowering::isFPExtFree(EVT DestVT, EVT SrcVT) const { in isFPExtFree() argument
16640 assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() && in isFPExtFree()
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/llvm-project-15.0.7/llvm/utils/TableGen/
H A DCallingConvEmitter.cpp294 MVT::SimpleValueType DestVT = getValueType(DestTy); in EmitAction() local
295 O << IndentStr << "LocVT = " << getEnumName(DestVT) <<";\n"; in EmitAction()
296 if (MVT(DestVT).isFloatingPoint()) { in EmitAction()
308 MVT::SimpleValueType DestVT = getValueType(DestTy); in EmitAction() local
309 O << IndentStr << "LocVT = " << getEnumName(DestVT) << ";\n"; in EmitAction()
310 if (MVT(DestVT).isFloatingPoint()) { in EmitAction()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp2804 MVT DestVT; in selectFPToInt() local
2805 if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector()) in selectFPToInt()
2837 MVT DestVT; in selectIntToFP() local
2844 assert((DestVT == MVT::f32 || DestVT == MVT::f64) && in selectIntToFP()
3885 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8 && in selectTrunc()
3933 assert((DestVT == MVT::i8 || DestVT == MVT::i16 || DestVT == MVT::i32 || in emiti1Ext()
3937 if (DestVT == MVT::i8 || DestVT == MVT::i16) in emiti1Ext()
4330 if (((DestVT != MVT::i8) && (DestVT != MVT::i16) && in emitIntExt()
4331 (DestVT != MVT::i32) && (DestVT != MVT::i64)) || in emitIntExt()
4366 if (DestVT == MVT::i8 || DestVT == MVT::i16) in emitIntExt()
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H A DAArch64ISelLowering.cpp9514 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts); in ReconstructShuffle() local
9521 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
9541 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
9547 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
9552 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
9555 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
9566 Src.ShuffleVec = DAG.getNode(AArch64ISD::EXT, dl, DestVT, VEXTSrc1, in ReconstructShuffle()
19828 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, in PerformDAGCombine() local
19831 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, DL, DestVT, Opnds); in PerformDAGCombine()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMFastISel.cpp1741 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1) in SelectBinaryIntOp()
1953 MVT DestVT = VA.getLocVT(); in ProcessCallArgs() local
1956 ArgVT = DestVT; in ProcessCallArgs()
1962 MVT DestVT = VA.getLocVT(); in ProcessCallArgs() local
1965 ArgVT = DestVT; in ProcessCallArgs()
2128 MVT DestVT = VA.getValVT(); in SelectRet() local
2130 if (RVVT != DestVT) { in SelectRet()
2585 EVT SrcVT, DestVT; in SelectTrunc() local
2591 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1) in SelectTrunc()
2605 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8) in ARMEmitIntExt()
[all …]
H A DARMISelLowering.cpp8152 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts); in ReconstructShuffle() local
8160 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
8176 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
8182 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
8187 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
8190 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
8193 Src.ShuffleVec = DAG.getNode(ARMISD::VEXT, dl, DestVT, VEXTSrc1, in ReconstructShuffle()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVECustomDAG.h190 SDValue getUnpack(EVT DestVT, SDValue Vec, PackElem Part, SDValue AVL) const;
191 SDValue getPack(EVT DestVT, SDValue LoVec, SDValue HiVec, SDValue AVL) const;
H A DVECustomDAG.cpp480 SDValue VECustomDAG::getUnpack(EVT DestVT, SDValue Vec, PackElem Part, in getUnpack() argument
487 return DAG.getNode(OC, DL, DestVT, Vec, AVL); in getUnpack()
490 SDValue VECustomDAG::getPack(EVT DestVT, SDValue LoVec, SDValue HiVec, in getPack() argument
495 return DAG.getNode(VEISD::VEC_PACK, DL, DestVT, LoVec, HiVec, AVL); in getPack()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp876 EVT DestVT = Node->getValueType(0); in LegalizeLoadOps() local
1746 (SlotVT.bitsLT(DestVT) && in EmitStackConvert()
1773 if (SlotVT.bitsEq(DestVT)) in EmitStackConvert()
2323 EVT DestVT = Node->getValueType(0); in ExpandLegalINT_TO_FP() local
2332 (DestVT.bitsLE(MVT::f64) || in ExpandLegalINT_TO_FP()
2335 DestVT))) { in ExpandLegalINT_TO_FP()
2507 if (DestVT == MVT::f32) in ExpandLegalINT_TO_FP()
2542 EVT DestVT = N->getValueType(0); in PromoteLegalINT_TO_FP() local
2588 DAG.getNode(OpToUse, dl, DestVT, in PromoteLegalINT_TO_FP()
2603 EVT DestVT = N->getValueType(0); in PromoteLegalFP_TO_INT() local
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H A DLegalizeTypes.cpp895 EVT DestVT) { in CreateStackStoreLoad() argument
902 Align DestAlign = DAG.getReducedAlign(DestVT, /*UseABI=*/false); in CreateStackStoreLoad()
911 return DAG.getLoad(DestVT, dl, Store, StackPtr, MachinePointerInfo(), Align); in CreateStackStoreLoad()
H A DSelectionDAGBuilder.cpp3225 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode)); in visitICmp()
3401 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N)); in visitTrunc()
3427 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); in visitFPTrunc() local
3428 setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N, in visitFPTrunc()
3483 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT); in visitPtrToInt()
3492 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); in visitIntToPtr() local
3495 N = DAG.getPtrExtOrTrunc(N, getCurSDLoc(), DestVT); in visitIntToPtr()
3507 if (DestVT != N.getValueType()) in visitBitCast()
3509 DestVT, N)); // convert types. in visitBitCast()
3525 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); in visitAddrSpaceCast() local
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H A DLegalizeVectorTypes.cpp384 EVT DestVT = N->getValueType(0).getVectorElementType(); in ScalarizeVecRes_UnaryOp() local
402 return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op, N->getFlags()); in ScalarizeVecRes_UnaryOp()
2183 EVT DestVT = N->getValueType(0); in SplitVecRes_ExtendOp() local
2185 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(DestVT); in SplitVecRes_ExtendOp()
2201 SrcVT.getScalarSizeInBits() * 2 < DestVT.getScalarSizeInBits()) { in SplitVecRes_ExtendOp()
H A DLegalizeTypes.h219 SDValue CreateStackStoreLoad(SDValue Op, EVT DestVT);
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp2439 EVT DestVT = Op.getValueType(); in LowerUINT_TO_FP() local
2444 if (DestVT == MVT::f16) in LowerUINT_TO_FP()
2466 if (DestVT == MVT::f32) in LowerUINT_TO_FP()
2469 assert(DestVT == MVT::f64); in LowerUINT_TO_FP()
2475 EVT DestVT = Op.getValueType(); in LowerSINT_TO_FP() local
2481 if (DestVT == MVT::f16) in LowerSINT_TO_FP()
2506 if (DestVT == MVT::f32) in LowerSINT_TO_FP()
2509 assert(DestVT == MVT::f64); in LowerSINT_TO_FP()
2690 EVT DestVT = Op.getValueType(); in LowerFP_TO_INT() local
3957 if (DestVT.isVector()) { in PerformDAGCombine()
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H A DSIISelLowering.h265 bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT,
H A DSIISelLowering.cpp790 EVT DestVT, EVT SrcVT) const { in isFPExtFoldable() argument
793 DestVT.getScalarType() == MVT::f32 && in isFPExtFoldable()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1134 MVT DestVT = TLI->getRegisterType(NewVT); in getVectorTypeBreakdownMVT() local
1135 RegisterVT = DestVT; in getVectorTypeBreakdownMVT()
1136 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. in getVectorTypeBreakdownMVT()
1137 return NumVectorRegs * (LaneSizeInBits / DestVT.getScalarSizeInBits()); in getVectorTypeBreakdownMVT()
1606 MVT DestVT = getRegisterType(Context, NewVT); in getVectorTypeBreakdown() local
1607 RegisterVT = DestVT; in getVectorTypeBreakdown()
1609 if (EVT(DestVT).bitsLT(NewVT)) { // Value is expanded, e.g. i64 -> i16. in getVectorTypeBreakdown()
1614 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); in getVectorTypeBreakdown()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetLowering.h2428 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { in AddPromotedToType() argument
2429 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy; in AddPromotedToType()
2434 void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { in setOperationPromotedToType() argument
2436 AddPromotedToType(Opc, OrigVT, DestVT); in setOperationPromotedToType()
2860 virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const { in isFPExtFree() argument
2861 assert(SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() && in isFPExtFree()
2878 EVT DestVT, EVT SrcVT) const { in isFPExtFoldable() argument
2879 assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() && in isFPExtFoldable()
2881 return isFPExtFree(DestVT, SrcVT); in isFPExtFoldable()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp20776 MVT DestVT = Cast.getSimpleValueType(); in vectorizeExtractedCast() local
20786 MVT ToVT = MVT::getVectorVT(DestVT, NumEltsInXMM); in vectorizeExtractedCast()
20806 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, DestVT, VCast, in vectorizeExtractedCast()
25497 MVT DestVT = VT == MVT::v2i64 ? MVT::v4i32 : VT; in LowerEXTEND_VECTOR_INREG() local
25499 unsigned DestWidth = DestVT.getScalarSizeInBits(); in LowerEXTEND_VECTOR_INREG()
25503 unsigned DestElts = DestVT.getVectorNumElements(); in LowerEXTEND_VECTOR_INREG()
25512 Curr = DAG.getBitcast(DestVT, Curr); in LowerEXTEND_VECTOR_INREG()
25515 SignExt = DAG.getNode(X86ISD::VSRAI, dl, DestVT, Curr, in LowerEXTEND_VECTOR_INREG()