232   unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
233   unsigned emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt);
2804   MVT DestVT;  in selectFPToInt()  local
2805   if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())  in selectFPToInt()
2819       Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWDr : AArch64::FCVTZSUXDr;  in selectFPToInt()
2821       Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWDr : AArch64::FCVTZUUXDr;  in selectFPToInt()
2824       Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWSr : AArch64::FCVTZSUXSr;  in selectFPToInt()
2826       Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWSr : AArch64::FCVTZUUXSr;  in selectFPToInt()
2829       DestVT == MVT::i32 ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass);  in selectFPToInt()
2837   MVT DestVT;  in selectIntToFP()  local
2838   if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())  in selectIntToFP()
2841   if (DestVT == MVT::f16)  in selectIntToFP()
2844   assert((DestVT == MVT::f32 || DestVT == MVT::f64) &&  in selectIntToFP()
2864       Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUXSri : AArch64::SCVTFUXDri;  in selectIntToFP()
2866       Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUXSri : AArch64::UCVTFUXDri;  in selectIntToFP()
2869       Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUWSri : AArch64::SCVTFUWDri;  in selectIntToFP()
2871       Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUWSri : AArch64::UCVTFUWDri;  in selectIntToFP()
2874   Register ResultReg = fastEmitInst_r(Opc, TLI.getRegClassFor(DestVT), SrcReg);  in selectIntToFP()
3021       MVT DestVT = VA.getLocVT();  in processCallArgs()  local
3023       ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);  in processCallArgs()
3031       MVT DestVT = VA.getLocVT();  in processCallArgs()  local
3033       ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);  in processCallArgs()
3832     MVT DestVT = VA.getValVT();  in selectRet()  local
3834     if (RVVT != DestVT) {  in selectRet()
3842       SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt);  in selectRet()
3880   MVT DestVT = DestEVT.getSimpleVT();  in selectTrunc()  local
3885   if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8 &&  in selectTrunc()
3886       DestVT != MVT::i1)  in selectTrunc()
3901     switch (DestVT.SimpleTy) {  in selectTrunc()
3932 unsigned AArch64FastISel::emiti1Ext(unsigned SrcReg, MVT DestVT, bool IsZExt) {  in emiti1Ext()  argument
3933   assert((DestVT == MVT::i8 || DestVT == MVT::i16 || DestVT == MVT::i32 ||  in emiti1Ext()
3934           DestVT == MVT::i64) &&  in emiti1Ext()
3937   if (DestVT == MVT::i8 || DestVT == MVT::i16)  in emiti1Ext()
3938     DestVT = MVT::i32;  in emiti1Ext()
3943     if (DestVT == MVT::i64) {  in emiti1Ext()
3956     if (DestVT == MVT::i64) {  in emiti1Ext()
4322 unsigned AArch64FastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,  in emitIntExt()  argument
4324   assert(DestVT != MVT::i1 && "ZeroExt/SignExt an i1?");  in emitIntExt()
4330   if (((DestVT != MVT::i8) && (DestVT != MVT::i16) &&  in emitIntExt()
4331        (DestVT != MVT::i32) && (DestVT != MVT::i64)) ||  in emitIntExt()
4343     return emiti1Ext(SrcReg, DestVT, IsZExt);  in emitIntExt()
4345     if (DestVT == MVT::i64)  in emitIntExt()
4352     if (DestVT == MVT::i64)  in emitIntExt()
4359     assert(DestVT == MVT::i64 && "IntExt i32 to i32?!?");  in emitIntExt()
4366   if (DestVT == MVT::i8 || DestVT == MVT::i16)  in emitIntExt()
4367     DestVT = MVT::i32;  in emitIntExt()
4368   else if (DestVT == MVT::i64) {  in emitIntExt()
4379       (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitIntExt()
4536   MVT DestVT = DestEVT.getSimpleVT();  in selectRem()  local
4537   if (DestVT != MVT::i64 && DestVT != MVT::i32)  in selectRem()
4541   bool Is64bit = (DestVT == MVT::i64);  in selectRem()
4562       (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in selectRem()