833 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {  in isNarrowingProfitable()
840   return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;  in isNarrowingProfitable()
2439   EVT DestVT = Op.getValueType();  in LowerUINT_TO_FP()  local
2444     if (DestVT == MVT::f16)  in LowerUINT_TO_FP()
2450     return DAG.getNode(ISD::UINT_TO_FP, DL, DestVT, Ext);  in LowerUINT_TO_FP()
2455   if (Subtarget->has16BitInsts() && DestVT == MVT::f16) {  in LowerUINT_TO_FP()
2466   if (DestVT == MVT::f32)  in LowerUINT_TO_FP()
2469   assert(DestVT == MVT::f64);  in LowerUINT_TO_FP()
2475   EVT DestVT = Op.getValueType();  in LowerSINT_TO_FP()  local
2481     if (DestVT == MVT::f16)  in LowerSINT_TO_FP()
2487     return DAG.getNode(ISD::SINT_TO_FP, DL, DestVT, Ext);  in LowerSINT_TO_FP()
2494   if (Subtarget->has16BitInsts() && DestVT == MVT::f16) {  in LowerSINT_TO_FP()
2506   if (DestVT == MVT::f32)  in LowerSINT_TO_FP()
2509   assert(DestVT == MVT::f64);  in LowerSINT_TO_FP()
2690   EVT DestVT = Op.getValueType();  in LowerFP_TO_INT()  local
2693   if (SrcVT == MVT::f16 && DestVT == MVT::i16)  in LowerFP_TO_INT()
2697   if (DestVT == MVT::i16 && (SrcVT == MVT::f32 || SrcVT == MVT::f64)) {  in LowerFP_TO_INT()
2714   if (DestVT == MVT::i64 && (SrcVT == MVT::f32 || SrcVT == MVT::f64))  in LowerFP_TO_INT()
3950     EVT DestVT = N->getValueType(0);  in PerformDAGCombine()  local
3957     if (DestVT.isVector()) {  in PerformDAGCombine()
3961         unsigned NElts = DestVT.getVectorNumElements();  in PerformDAGCombine()
3964           EVT DestEltVT = DestVT.getVectorElementType();  in PerformDAGCombine()
3973           return DAG.getBuildVector(DestVT, SL, CastedElts);  in PerformDAGCombine()
3978     if (DestVT.getSizeInBits() != 64 || !DestVT.isVector())  in PerformDAGCombine()
3992       return DAG.getNode(ISD::BITCAST, SL, DestVT, BV);  in PerformDAGCombine()
4003       return DAG.getNode(ISD::BITCAST, SL, DestVT, Vec);  in PerformDAGCombine()