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Searched refs:BaseOffs (Results 1 – 20 of 20) sorted by relevance

/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp2492 if (BaseOffs != other.BaseOffs) in compare()
2565 BaseOffs = 0; in SetCombinedField()
2591 if (BaseOffs) { in print()
2593 << BaseOffs; in print()
3957 if (AddrMode.BaseOffs) { in matchScaledValue()
4626 AddrMode.BaseOffs += ConstantOffset; in matchOperationAddr()
4656 AddrMode.BaseOffs -= ConstantOffset; in matchOperationAddr()
4665 AddrMode.BaseOffs += ConstantOffset; in matchOperationAddr()
4692 AddrMode.BaseOffs += ConstantOffset; in matchOperationAddr()
5354 if (AddrMode.BaseOffs) { in optimizeMemoryInst()
[all …]
H A DTargetLoweringBase.cpp1941 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) in isLegalAddressingMode()
1953 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
1958 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
/llvm-project-15.0.7/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1885 return AM.Scale == 0 && isImmUs(AM.BaseOffs) && isImmUs4(AM.BaseOffs); in isLegalAddressingMode()
1890 AM.BaseOffs%4 == 0; in isLegalAddressingMode()
1897 return isImmUs(AM.BaseOffs); in isLegalAddressingMode()
1900 return AM.Scale == 1 && AM.BaseOffs == 0; in isLegalAddressingMode()
1905 return isImmUs2(AM.BaseOffs); in isLegalAddressingMode()
1908 return AM.Scale == 2 && AM.BaseOffs == 0; in isLegalAddressingMode()
1912 return isImmUs4(AM.BaseOffs); in isLegalAddressingMode()
1915 return AM.Scale == 4 && AM.BaseOffs == 0; in isLegalAddressingMode()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUPerfHintAnalysis.cpp260 auto *Ptr = GetPointerBaseWithConstantOffset(GEP, AM.BaseOffs, *DL); in visit()
H A DSILoadStoreOptimizer.cpp2080 AM.BaseOffs = Dist; in promoteConstantOffsetToImm()
2105 AM.BaseOffs = P.second - AnchorAddr.Offset; in promoteConstantOffsetToImm()
H A DSIISelLowering.cpp1205 return AM.BaseOffs == 0 && AM.Scale == 0; in isLegalFlatAddressingMode()
1209 (AM.BaseOffs == 0 || in isLegalFlatAddressingMode()
1211 AM.BaseOffs, AMDGPUAS::FLAT_ADDRESS, SIInstrFlags::FLAT)); in isLegalFlatAddressingMode()
1218 AM.BaseOffs, AMDGPUAS::GLOBAL_ADDRESS, in isLegalGlobalAddressingMode()
1247 if (!SIInstrInfo::isLegalMUBUFImmOffset(AM.BaseOffs)) in isLegalMUBUFAddressingMode()
1288 if (AM.BaseOffs % 4 != 0) in isLegalAddressingMode()
1300 if (!isUInt<8>(AM.BaseOffs / 4)) in isLegalAddressingMode()
1305 if (!isUInt<32>(AM.BaseOffs / 4)) in isLegalAddressingMode()
1309 if (!isUInt<20>(AM.BaseOffs)) in isLegalAddressingMode()
1330 if (!isUInt<16>(AM.BaseOffs)) in isLegalAddressingMode()
[all …]
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp1373 AMNew.BaseOffs = CombinedImm.getSExtValue(); in matchPtrAddImmedChain()
1377 AMOld.BaseOffs = MaybeImm2Val->Value.getSExtValue(); in matchPtrAddImmedChain()
1387 MatchInfo.Imm = AMNew.BaseOffs; in matchPtrAddImmedChain()
4493 AM.BaseOffs = C2APIntVal.getSExtValue(); in reassociationCanBreakAddressingModePattern()
4505 AM.BaseOffs = CombinedValue; in reassociationCanBreakAddressingModePattern()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DBasicTTIImpl.h313 AM.BaseOffs = BaseOffset;
368 AM.BaseOffs = BaseOffset; in getScalingFactorCost()
H A DTargetLowering.h2516 int64_t BaseOffs = 0; member
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp3446 if (!isAligned(A, AM.BaseOffs)) in isLegalAddressingMode()
3449 if (!isInt<11>(AM.BaseOffs >> Log2(A))) in isLegalAddressingMode()
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp904 int64_t Offs = AM.BaseOffs; in isLegalAddressingMode()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp771 if (AM.BaseOffs < 0) in isLegalAddressingMode()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp16295 if (Ty->isVectorTy() && AM.BaseOffs != 0 && !Subtarget.hasP9Vector()) in isLegalAddressingMode()
16299 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) in isLegalAddressingMode()
16311 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
16316 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp978 if (!isInt<20>(AM.BaseOffs)) in isLegalAddressingMode()
986 if (!SupportedAM.LongDisplacement && !isUInt<12>(AM.BaseOffs)) in isLegalAddressingMode()
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp4369 return !AM.BaseOffs && !AM.HasBaseReg && !AM.Scale; in isLegalAddressingMode()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp1042 AM.BaseOffs = C2APIntVal.getSExtValue(); in reassociationCanBreakAddressingModePattern()
1050 AM.BaseOffs = CombinedValue; in reassociationCanBreakAddressingModePattern()
1069 AM.BaseOffs = C2APIntVal.getSExtValue(); in reassociationCanBreakAddressingModePattern()
2155 AM.BaseOffs = Offset->getSExtValue(); in canFoldInAddressingMode()
2164 AM.BaseOffs = -Offset->getSExtValue(); in canFoldInAddressingMode()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp1063 return AM.HasBaseReg && AM.Scale == 0 && !AM.BaseOffs; in isLegalAddressingMode()
1066 if (!isInt<12>(AM.BaseOffs)) in isLegalAddressingMode()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp13539 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale) in isLegalAddressingMode()
13546 return AM.HasBaseReg && !AM.BaseOffs && in isLegalAddressingMode()
13561 int64_t Offset = AM.BaseOffs; in isLegalAddressingMode()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp19370 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget)) in isLegalAddressingMode()
19382 if (AM.BaseOffs) in isLegalAddressingMode()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp33848 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr)) in isLegalAddressingMode()
33865 Subtarget.is64Bit() && (AM.BaseOffs || AM.Scale > 1)) in isLegalAddressingMode()