| /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/ |
| H A D | addc-adde-sube-subc.ll | 5 ; Ensure that the ISDOpcodes ADDC, ADDE, SUBC, SUBE are handled correctly
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| /llvm-project-15.0.7/llvm/lib/Target/Lanai/ |
| H A D | LanaiAluCode.h | 122 case ISD::ADDE: in isdToLanaiAluCode()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCBack2BackFusion.def | 15 ADDE,
500 ADDE,
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| H A D | P10InstrResources.td | 983 ADDE, ADDE8,
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| /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/ |
| H A D | aix-cc-byval-split.ll | 49 ; CHECK32: renamable $r3 = ADDE killed renamable $r7, killed renamable $r[[REG2]], implicit-def…
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 279 ADDE, enumerator
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| H A D | TargetLowering.h | 2622 case ISD::ADDE: in isCommutativeBinOp()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelDAGToDAG.cpp | 220 assert(Opc == ISD::ADDE && "ISD::ADDE not in a chain of ADDE nodes!"); in selectAddE()
764 case ISD::ADDE: { in trySelect()
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| H A D | MipsSEISelLowering.cpp | 107 setOperationAction(ISD::ADDE, MVT::i32, Legal); in MipsSETargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1656 setOperationAction(ISD::ADDE, MVT::i32, Custom); in SparcTargetLowering()
1662 setOperationAction(ISD::ADDE, MVT::i64, Custom); in SparcTargetLowering()
3016 case ISD::ADDC: hiOpc = ISD::ADDE; break; in LowerADDC_ADDE_SUBC_SUBE()
3017 case ISD::ADDE: hasChain = true; break; in LowerADDC_ADDE_SUBC_SUBE()
3173 case ISD::ADDE: in LowerOperation()
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| H A D | SparcInstrInfo.td | 792 defm ADDE : F3_12<"addxcc", 0b011000, adde, IntRegs, i32, simm13Op>;
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 109 ADDE, // Add using carry enumerator
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| H A D | ARMISelLowering.cpp | 1706 MAKE_CASE(ARMISD::ADDE) in getTargetNodeName()
4980 return DAG.getNode(ARMISD::ADDE, DL, DAG.getVTList(VT, MVT::i32), in ConvertCarryFlagToBooleanCarry()
9740 Result = DAG.getNode(ARMISD::ADDE, DL, VTs, Op.getOperand(0), in LowerADDSUBCARRY()
12687 assert((AddeSubeNode->getOpcode() == ARMISD::ADDE || in AddCombineTo64bitMLAL()
12697 if ((AddeSubeNode->getOpcode() == ARMISD::ADDE && in AddCombineTo64bitMLAL()
12716 if (AddeSubeNode->getOpcode() == ARMISD::ADDE && in AddCombineTo64bitMLAL()
12895 (AddeNode->getOpcode() == ARMISD::ADDE) && in PerformUMLALCombine()
12916 if (LHS->getOpcode() == ARMISD::ADDE && in PerformAddcSubcCombine()
18590 case ARMISD::ADDE: return PerformADDECombine(N, DCI, Subtarget); in PerformDAGCombine()
19784 case ARMISD::ADDE: in computeKnownBitsForTargetNode()
[all …]
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 304 case ISD::ADDE: return "adde"; in getOperationName()
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| H A D | LegalizeIntegerTypes.cpp | 185 case ISD::ADDE: in PromoteIntegerResult()
2500 case ISD::ADDE: in ExpandIntegerResult()
2943 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps); in ExpandIntRes_ADDSUB()
3040 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps); in ExpandIntRes_ADDSUBC()
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| H A D | TargetLowering.cpp | 7069 isOperationLegalOrCustom(ISD::ADDE, VT)); in expandMUL_LOHI()
7085 Hi = DAG.getNode(ISD::ADDE, dl, DAG.getVTList(HiLoVT, MVT::Glue), Hi, Zero, in expandMUL_LOHI()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 534 case ISD::ADDE: in Select()
835 bool ConsumeCarry = (Opcode == ISD::ADDE || Opcode == ISD::SUBE); in SelectADD_SUB_I64()
838 bool IsAdd = Opcode == ISD::ADD || Opcode == ISD::ADDC || Opcode == ISD::ADDE; in SelectADD_SUB_I64()
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| H A D | R600ISelLowering.cpp | 186 setOperationAction({ISD::ADDC, ISD::SUBC, ISD::ADDE, ISD::SUBE}, VT, in R600TargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/ARC/ |
| H A D | ARCISelLowering.cpp | 125 setOperationAction(ISD::ADDE, MVT::i32, Legal); in ARCTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 110 setOperationAction(ISD::ADDE, VT, Custom); in M68kTargetLowering()
1342 case ISD::ADDE: in LowerOperation()
2474 case ISD::ADDE: in LowerADDC_ADDE_SUBC_SUBE()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 824 setOperationAction({ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}, VT, in initActions()
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| /llvm-project-15.0.7/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 525 setOperationAction(ISD::ADDE, MVT::i32, Legal); in NVPTXTargetLowering()
530 setOperationAction(ISD::ADDE, MVT::i64, Legal); in NVPTXTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 72 setOperationAction(ISD::ADDE, VT, Legal); in AVRTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 145 ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}) { in WebAssemblyTargetLowering()
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| /llvm-project-15.0.7/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 407 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
|