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Searched refs:TII (Results 1 – 25 of 440) sorted by relevance

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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kExpandPseudo.cpp106 return TII->ExpandMOVSZX_RM(MIB, true, TII->get(M68k::MOV8dj), MVT::i16, in ExpandMI()
109 return TII->ExpandMOVSZX_RM(MIB, true, TII->get(M68k::MOV8dj), MVT::i32, in ExpandMI()
126 return TII->ExpandMOVSZX_RM(MIB, true, TII->get(M68k::MOV8dp), MVT::i16, in ExpandMI()
129 return TII->ExpandMOVSZX_RM(MIB, true, TII->get(M68k::MOV8dp), MVT::i32, in ExpandMI()
171 return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM32jm), /*IsRM=*/false); in ExpandMI()
185 return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM32mj), /*IsRM=*/true); in ExpandMI()
187 return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM32mj), /*IsRM=*/true); in ExpandMI()
189 return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM32mj), /*IsRM=*/true); in ExpandMI()
192 return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM32mp), /*IsRM=*/true); in ExpandMI()
194 return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM32mp), /*IsRM=*/true); in ExpandMI()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyLowerBrUnless.cpp81 Def->setDesc(TII.get(NE_I32)); in runOnMachineFunction()
85 Def->setDesc(TII.get(EQ_I32)); in runOnMachineFunction()
89 Def->setDesc(TII.get(LE_S_I32)); in runOnMachineFunction()
93 Def->setDesc(TII.get(LT_S_I32)); in runOnMachineFunction()
97 Def->setDesc(TII.get(GE_S_I32)); in runOnMachineFunction()
121 Def->setDesc(TII.get(NE_I64)); in runOnMachineFunction()
125 Def->setDesc(TII.get(EQ_I64)); in runOnMachineFunction()
161 Def->setDesc(TII.get(NE_F32)); in runOnMachineFunction()
165 Def->setDesc(TII.get(EQ_F32)); in runOnMachineFunction()
169 Def->setDesc(TII.get(NE_F64)); in runOnMachineFunction()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIPeepholeSDWA.cpp49 const SIInstrInfo *TII; member in __anon361dcac40111::SIPeepholeSDWA
505 if (!TII->isFoldableCopy(*DefInst)) in foldToImm()
705 if (!TII->isSDWA(*Op1Inst)) in matchSDWAOperand()
755 if (!TII->isSDWA(*OtherInst)) in matchSDWAOperand()
860 if (!TII->canShrink(MI, *MRI)) in pseudoOpConvertToVOP2()
872 if (!TII->canShrink(MISucc, *MRI)) in pseudoOpConvertToVOP2()
920 if (TII->isSDWA(Opc)) in isConvertibleToSDWA()
933 if (TII->isVOPC(Opc)) { in isConvertibleToSDWA()
958 if (TII->pseudoToMCOpcode(Opc) == -1) in isConvertibleToSDWA()
986 if (TII->isSDWA(Opcode)) { in convertToSDWA()
[all …]
H A DR600ExpandSpecialInstrs.cpp29 const R600InstrInfo *TII = nullptr; member in __anon8796a7730111::R600ExpandSpecialInstrsPass
63 int OpIdx = TII->getOperandIdx(*OldMI, Op); in SetFlagInNewMI()
66 TII->setImmOperand(*NewMI, Op, Val); in SetFlagInNewMI()
72 TII = ST.getInstrInfo(); in runOnMachineFunction()
85 if (TII->isLDSRetInstr(MI.getOpcode())) { in runOnMachineFunction()
113 TII->addFlag(*PredSet, 0, MO_FLAG_MASK); in runOnMachineFunction()
139 TII->addFlag(*BMI, 0, MO_FLAG_MASK); in runOnMachineFunction()
142 TII->addFlag(*BMI, 0, MO_FLAG_NOT_LAST); in runOnMachineFunction()
164 bool IsVector = TII->isVector(MI); in runOnMachineFunction()
165 bool IsCube = TII->isCubeOp(MI.getOpcode()); in runOnMachineFunction()
[all …]
H A DSIShrinkInstructions.cpp64 assert(TII->isVOP1(MI) || TII->isVOP2(MI) || TII->isVOPC(MI)); in foldImmediates()
105 if (TII->commuteInstruction(MI)) { in foldImmediates()
110 TII->commuteInstruction(MI); in foldImmediates()
134 return !TII->isInlineConstant(Src); in isKImmOrKUImmOperand()
139 return !TII->isInlineConstant(Src); in isKImmOrKUImmOperand()
200 MI.setDesc(TII->get(SOPKOpc)); in shrinkScalarCompare()
208 if ((TII->sopkIsZext(SOPKOpc) && isKUImmOperand(TII, Src1)) || in shrinkScalarCompare()
209 (!TII->sopkIsZext(SOPKOpc) && isKImmOperand(TII, Src1))) { in shrinkScalarCompare()
294 MI.setDesc(TII->get(NewOpcode)); in shrinkMIMG()
373 MI.setDesc(TII->get(Opc)); in shrinkScalarLogicOp()
[all …]
H A DSIFoldOperands.cpp82 const SIInstrInfo *TII; member in __anon3d458c240111::SIFoldOperands
182 if (TII->isMUBUF(UseMI)) in frameIndexMayFold()
185 if (!TII->isFLATScratch(UseMI)) in frameIndexMayFold()
357 MI->setDesc(TII->get(NewOpc)); in tryAddToFoldList()
363 MI->setDesc(TII->get(Opc)); in tryAddToFoldList()
449 if (TII->isSALU(MI->getOpcode())) { in tryAddToFoldList()
652 if (TII->isMUBUF(*UseMI)) { in foldOperand()
729 UseMI->setDesc(TII->get(MovOp)); in foldOperand()
1378 if (TII->getClampMask(*Def) != TII->getClampMask(MI)) in tryFoldClamp()
1730 TII = ST->getInstrInfo(); in runOnMachineFunction()
[all …]
H A DR600Packetizer.cpp52 const R600InstrInfo *TII; member in __anone5f429810111::R600PacketizerList
79 if (TII->isPredicated(*BI)) in getPreviousVector()
145 TII(ST.getInstrInfo()), in R600PacketizerList()
146 TRI(TII->getRegisterInfo()) { in R600PacketizerList()
164 if (TII->isVector(MI)) in isSoloInstruction()
166 if (!TII->isALUInstr(MI.getOpcode())) in isSoloInstruction()
172 return TII->isLDSInstr(MI.getOpcode()); in isSoloInstruction()
203 TII->definesAddressRegister(*MII) || TII->definesAddressRegister(*MIJ); in isLegalToPacketizeTogether()
205 TII->usesAddressRegister(*MII) || TII->usesAddressRegister(*MIJ); in isLegalToPacketizeTogether()
225 isTransSlot = TII->isTransOnly(MI); in isBundlableWithCurrentPMI()
[all …]
H A DGCNDPPCombine.cpp56 const SIInstrInfo *TII; member in __anonb4df09800111::GCNDPPCombine
119 if (!TII->isVOP3(Op)) { in isShrinkable()
122 if (!TII->hasVALU32BitEncoding(Op)) { in isShrinkable()
196 OrigMI.getDebugLoc(), TII->get(DPPOp)) in createDPPInst()
226 if (auto *Mod0 = TII->getNamedOperand(OrigMI, in createDPPInst()
249 if (auto *Mod1 = TII->getNamedOperand(OrigMI, in createDPPInst()
376 auto *Imm = TII->getNamedOperand(MI, OpndName); in hasNoImmOrEqual()
535 if (!(IsShrinkable || TII->isVOP1(OrigOp) || TII->isVOP2(OrigOp))) { in combineDPPMov()
569 if (TII->commuteInstruction(*NewMI)) { in combineDPPMov()
611 TII = ST->getInstrInfo(); in runOnMachineFunction()
[all …]
H A DSIModeRegister.cpp146 const SIInstrInfo *TII, Status InstrMode);
165 if (TII->usesFPDPRounding(MI)) { in getInstructionMode()
191 BuildMI(MBB, MI, 0, TII->get(AMDGPU::S_SETREG_IMM32_B32)) in insertSetreg()
222 const SIInstrInfo *TII) { in processBlockPhase1() argument
233 Status InstrMode = getInstructionMode(MI, TII); in processBlockPhase1()
289 insertSetreg(MBB, InsertionPoint, TII, in processBlockPhase1()
400 insertSetreg(MBB, &MBB.instr_front(), TII, Delta); in processBlockPhase3()
407 const SIInstrInfo *TII = ST.getInstrInfo(); in runOnMachineFunction() local
414 processBlockPhase1(BB, TII); in runOnMachineFunction()
422 processBlockPhase2(*Phase2List.front(), TII); in runOnMachineFunction()
[all …]
H A DSILoadStoreOptimizer.cpp286 if (TII.isMUBUF(Opc)) { in getOpcodeWidth()
290 if (TII.isMIMG(MI)) { in getOpcodeWidth()
295 if (TII.isMTBUF(Opc)) { in getOpcodeWidth()
341 if (TII.isMIMG(Opc)) { in getInstClass()
347 if (TII.get(Opc).mayStore() || !TII.get(Opc).mayLoad() || in getInstClass()
400 if (TII.isMUBUF(Opc)) in getInstSubclass()
402 if (TII.isMIMG(Opc)) { in getInstSubclass()
407 if (TII.isMTBUF(Opc)) in getInstSubclass()
429 if (TII.isMUBUF(Opc)) { in getRegs()
440 if (TII.isMIMG(Opc)) { in getRegs()
[all …]
H A DR600EmitClauseMarkers.cpp33 const R600InstrInfo *TII = nullptr; member in __anonee5cdf500111::R600EmitClauseMarkers
51 if (TII->isLDSRetInstr(MI.getOpcode())) in OccupiedDwords()
54 if (TII->isVector(MI) || TII->isCubeOp(MI.getOpcode()) || in OccupiedDwords()
55 TII->isReductionOp(MI.getOpcode())) in OccupiedDwords()
70 if (TII->isALUInstr(MI.getOpcode())) in isALU()
72 if (TII->isVector(MI) || TII->isCubeOp(MI.getOpcode())) in isALU()
122 TII->getSrcs(MI); in SubstituteKCacheBank()
203 if (AluInstCount >= TII->getMaxAlusPerClause()) in canClauseLocalKillFitInClause()
237 if (AluInstCount > TII->getMaxAlusPerClause()) in MakeALUClause()
260 if (TII->mustBeLastInClause(I->getOpcode())) { in MakeALUClause()
[all …]
H A DR600ClauseMergePass.cpp38 const R600InstrInfo *TII; member in __anon899078730111::R600ClauseMergePass
114 if (CumuledInsts >= TII->getMaxAlusPerClause()) { in mergeIfPossible()
122 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_MODE0); in mergeIfPossible()
124 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_BANK0); in mergeIfPossible()
126 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_ADDR0); in mergeIfPossible()
138 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_MODE1); in mergeIfPossible()
140 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_BANK1); in mergeIfPossible()
169 RootCFAlu.setDesc(TII->get(LatrCFAlu.getOpcode())); in mergeIfPossible()
178 TII = ST.getInstrInfo(); in runOnMachineFunction()
187 if ((!TII->canBeConsideredALU(MI) && !isCFAlu(MI)) || in runOnMachineFunction()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DPseudoSourceValue.cpp29 AddressSpace = TII.getAddressSpaceForPseudoSourceKind(Kind); in PseudoSourceValue()
83 unsigned Kind, const TargetInstrInfo &TII) in CallEntryPseudoSourceValue() argument
84 : PseudoSourceValue(Kind, TII) {} in CallEntryPseudoSourceValue()
100 const TargetInstrInfo &TII) in GlobalValuePseudoSourceValue() argument
103 const char *ES, const TargetInstrInfo &TII) in ExternalSymbolPseudoSourceValue() argument
108 : TII(TIInfo), in PseudoSourceValueManager()
109 StackPSV(PseudoSourceValue::Stack, TII), in PseudoSourceValueManager()
110 GOTPSV(PseudoSourceValue::GOT, TII), in PseudoSourceValueManager()
111 JumpTablePSV(PseudoSourceValue::JumpTable, TII), in PseudoSourceValueManager()
112 ConstantPoolPSV(PseudoSourceValue::ConstantPool, TII) {} in PseudoSourceValueManager()
[all …]
H A DXRayInstrumentation.cpp70 const TargetInstrInfo *TII,
82 const TargetInstrInfo *TII,
89 MachineFunction &MF, const TargetInstrInfo *TII, in replaceRetWithPatchableRet() argument
103 if (TII->isTailCall(T) && op.HandleTailcall) { in replaceRetWithPatchableRet()
125 MachineFunction &MF, const TargetInstrInfo *TII, in prependRetWithPatchableExit() argument
134 if (TII->isTailCall(T) && op.HandleTailcall) { in prependRetWithPatchableExit()
140 BuildMI(MBB, T, T.getDebugLoc(), TII->get(Opc)); in prependRetWithPatchableExit()
207 auto *TII = MF.getSubtarget().getInstrInfo(); in runOnMachineFunction() local
237 prependRetWithPatchableExit(MF, TII, op); in runOnMachineFunction()
245 replaceRetWithPatchableRet(MF, TII, op); in runOnMachineFunction()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstructionSelector.cpp61 const MipsInstrInfo &TII; member in __anonec165afe0111::MipsInstructionSelector
173 if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI)) in materialize32BitImm()
175 if (!constrainSelectedInstRegOperands(*ORi, TII, TRI, RBI)) in materialize32BitImm()
350 I.setDesc(TII.get(COPY)); in select()
391 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW)) in select()
435 I.setDesc(TII.get(TargetOpcode::PHI)); in select()
501 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(NewOpc)) in select()
605 if (!MTC1.constrainAllUses(TII, TRI, RBI)) in select()
620 if (!PairF64.constrainAllUses(TII, TRI, RBI)) in select()
814 if (!MIB.constrainAllUses(TII, TRI, RBI)) in select()
[all …]
H A DMipsBranchExpansion.cpp167 const MipsInstrInfo *TII; member in __anon3df5339e0111::MipsBranchExpansion
299 MBBInfos[I].Size += TII->getInstSizeInBytes(*MI); in initMBBInfo()
338 const MCInstrDesc &NewDesc = TII->get(NewOpc); in replaceBranch()
352 if (!TII->isBranchWithImm(Br->getOpcode())) in replaceBranch()
468 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)) in expandToLongBranch()
591 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SD)) in expandToLongBranch()
677 .append(BuildMI(*MFp, DL, TII->get(Mips::NOP))); in expandToLongBranch()
733 BuildMI(MBB, I, DL, TII->get(Mips::LUi), Mips::V0) in emitGPDisp()
735 BuildMI(MBB, I, DL, TII->get(Mips::ADDiu), Mips::V0) in emitGPDisp()
752 if (!TII->HasForbiddenSlot(*I)) in handleForbiddenSlot()
[all …]
H A DMipsExpandPseudo.cpp38 const MipsInstrInfo *TII; member in __anona523604b0111::MipsExpandPseudo
149 BuildMI(loop1MBB, DL, TII->get(BNE)) in expandAtomicCmpSwapSubword()
163 BuildMI(loop2MBB, DL, TII->get(SC), Scratch) in expandAtomicCmpSwapSubword()
167 BuildMI(loop2MBB, DL, TII->get(BEQ)) in expandAtomicCmpSwapSubword()
279 BuildMI(loop1MBB, DL, TII->get(BNE)) in expandAtomicCmpSwap()
287 BuildMI(loop2MBB, DL, TII->get(SC), Scratch) in expandAtomicCmpSwap()
289 BuildMI(loop2MBB, DL, TII->get(BEQ)) in expandAtomicCmpSwap()
539 BuildMI(loopMBB, DL, TII->get(BEQ)) in expandAtomicBinOpSubword()
797 BuildMI(loopMBB, DL, TII->get(SC), Scratch) in expandAtomicBinOp()
801 BuildMI(loopMBB, DL, TII->get(BEQ)) in expandAtomicBinOp()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVExpandAtomicPseudoInsts.cpp33 const RISCVInstrInfo *TII; member in __anon479d2dd50111::RISCVExpandAtomicPseudo
250 BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)) in doAtomicBinOpExpansion()
273 BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg) in insertMaskedMerge()
335 BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)) in doMaskedAtomicBinOpExpansion()
382 BuildMI(MBB, DL, TII->get(RISCV::SLL), ValReg) in insertSext()
385 BuildMI(MBB, DL, TII->get(RISCV::SRA), ValReg) in insertSext()
453 BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGE)) in expandAtomicMinMaxOp()
461 BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGE)) in expandAtomicMinMaxOp()
494 BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE)) in expandAtomicMinMaxOp()
549 BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BNE)) in expandAtomicCmpXchg()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRFrameLowering.cpp57 const AVRInstrInfo &TII = *STI.getInstrInfo(); in emitPrologue() local
63 BuildMI(MBB, MBBI, DL, TII.get(AVR::BSETs)) in emitPrologue()
71 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHWRr)) in emitPrologue()
78 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr)) in emitPrologue()
81 BuildMI(MBB, MBBI, DL, TII.get(AVR::EORRdRr)) in emitPrologue()
86 BuildMI(MBB, MBBI, DL, TII.get(AVR::EORRdRr)) in emitPrologue()
146 const AVRInstrInfo &TII = *STI.getInstrInfo(); in restoreStatusRegister() local
266 BuildMI(MBB, MI, DL, TII.get(AVR::PUSHRr)) in spillCalleeSavedRegisters()
326 MI.setDesc(TII.get(STOpc)); in fixStackStores()
343 fixStackStores(MBB, MI, TII, AVR::R29R28); in eliminateCallFramePseudoInstr()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430FrameLowering.cpp45 const MSP430InstrInfo &TII = in emitPrologue() local
66 BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r)) in emitPrologue()
70 BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::R4) in emitPrologue()
110 const MSP430InstrInfo &TII = in emitEpilogue() local
161 TII.get(MSP430::SUB16ri), MSP430::SP) in emitEpilogue()
197 BuildMI(MBB, MI, DL, TII.get(MSP430::PUSH16r)) in spillCalleeSavedRegisters()
224 const MSP430InstrInfo &TII = in eliminateCallFramePseudoInstr() local
232 uint64_t Amount = TII.getFrameSize(Old); in eliminateCallFramePseudoInstr()
240 if (Old.getOpcode() == TII.getCallFrameSetupOpcode()) { in eliminateCallFramePseudoInstr()
248 Amount -= TII.getFramePoppedByCallee(Old); in eliminateCallFramePseudoInstr()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreFrameLowering.cpp66 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in EmitDefCfaRegister()
107 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(OpImm); in IfNeededExtSP()
110 EmitDefCfaOffset(MBB, MBBI, dl, TII, Adjusted*4); in IfNeededExtSP()
269 EmitDefCfaOffset(MBB, MBBI, dl, TII, Adjusted*4); in emitPrologue()
271 EmitCfiOffset(MBB, MBBI, dl, TII, DRegNum, 0); in emitPrologue()
289 BuildMI(MBB, MBBI, dl, TII.get(Opcode)) in emitPrologue()
309 EmitDefCfaRegister(MBB, MBBI, dl, TII, MF, in emitPrologue()
321 EmitCfiOffset(MBB, Pos, dl, TII, DRegNum, Offset); in emitPrologue()
333 EmitCfiOffset(MBB, MBBI, dl, TII, in emitPrologue()
336 EmitCfiOffset(MBB, MBBI, dl, TII, in emitPrologue()
[all …]
H A DXCoreRegisterInfo.cpp62 const XCoreInstrInfo &TII, in InsertFPImmInst() argument
76 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus)) in InsertFPImmInst()
102 TII.loadImmediate(MBB, II, ScratchOffset, Offset); in InsertFPConstInst()
112 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r)) in InsertFPConstInst()
140 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst()
146 BuildMI(MBB, II, dl, TII.get(NewOpcode)) in InsertSPImmInst()
153 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst()
189 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r)) in InsertSPConstInst()
263 const XCoreInstrInfo &TII = in eliminateFrameIndex() local
309 InsertSPImmInst(II, TII, Reg, Offset); in eliminateFrameIndex()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEFrameLowering.cpp142 const VEInstrInfo &TII = *STI.getInstrInfo(); in emitPrologueInsns() local
152 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
157 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
164 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
169 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
176 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
190 const VEInstrInfo &TII = *STI.getInstrInfo(); in emitEpilogueInsns() local
232 const VEInstrInfo &TII = *STI.getInstrInfo(); in emitSPAdjustment() local
277 const VEInstrInfo &TII = *STI.getInstrInfo(); in emitSPExtend() local
313 const VEInstrInfo &TII = *STI.getInstrInfo(); in emitPrologue() local
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp73 const ARMBaseInstrInfo &TII; member in __anon9fac60cc0111::ARMInstructionSelector
256 MIB->setDesc(TII.get(ARM::VMOVDRR)); in selectMergeValues()
677 MIB->setDesc(TII.get(Opc)); in selectGlobal()
715 MIB->setDesc(TII.get(Opc)); in selectGlobal()
807 MIB->setDesc(TII.get(ARM::MOVsr)); in selectShift()
902 I.setDesc(TII.get(NewOpc)); in select()
958 I.setDesc(TII.get(COPY)); in select()
984 I.setDesc(TII.get(ARM::MOVi)); in select()
1030 I.setDesc(TII.get(COPY)); in select()
1099 I.setDesc(TII.get(NewOpc)); in select()
[all …]
H A DARMFrameLowering.cpp900 const ARMBaseInstrInfo &TII = in emitEpilogue() local
1016 emitSPUpdate(isARM, MBB, MBBI, dl, TII, in emitEpilogue()
1644 FnSize += TII.getInstSizeInBytes(MI); in EstimateFunctionSizeInBytes()
1661 const ARMBaseInstrInfo &TII = in estimateRSStackSizeLimit() local
1812 const ARMBaseInstrInfo &TII = in determineCalleeSaves() local
2331 const ARMBaseInstrInfo &TII = in eliminateCallFramePseudoInstr() local
2347 unsigned PredReg = TII.getFramePred(*I); in eliminateCallFramePseudoInstr()
2357 unsigned Amount = TII.getFrameSize(*I); in eliminateCallFramePseudoInstr()
2457 const ARMBaseInstrInfo &TII = in adjustForSegmentedStacks() local
2645 BuildMI(GetMBB, DL, TII.get(Opcode)) in adjustForSegmentedStacks()
[all …]

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