Lines Matching refs:TII
161 void setMI(MachineBasicBlock::iterator MI, const SIInstrInfo &TII,
182 const SIInstrInfo *TII = nullptr; member in __anon8de982330111::SILoadStoreOptimizer
189 const SIInstrInfo &TII,
283 static unsigned getOpcodeWidth(const MachineInstr &MI, const SIInstrInfo &TII) { in getOpcodeWidth() argument
286 if (TII.isMUBUF(Opc)) { in getOpcodeWidth()
290 if (TII.isMIMG(MI)) { in getOpcodeWidth()
292 TII.getNamedOperand(MI, AMDGPU::OpName::dmask)->getImm(); in getOpcodeWidth()
295 if (TII.isMTBUF(Opc)) { in getOpcodeWidth()
322 static InstClassEnum getInstClass(unsigned Opc, const SIInstrInfo &TII) { in getInstClass() argument
325 if (TII.isMUBUF(Opc)) { in getInstClass()
341 if (TII.isMIMG(Opc)) { in getInstClass()
347 if (TII.get(Opc).mayStore() || !TII.get(Opc).mayLoad() || in getInstClass()
348 TII.isGather4(Opc)) in getInstClass()
352 if (TII.isMTBUF(Opc)) { in getInstClass()
397 static unsigned getInstSubclass(unsigned Opc, const SIInstrInfo &TII) { in getInstSubclass() argument
400 if (TII.isMUBUF(Opc)) in getInstSubclass()
402 if (TII.isMIMG(Opc)) { in getInstSubclass()
407 if (TII.isMTBUF(Opc)) in getInstSubclass()
426 static AddressRegs getRegs(unsigned Opc, const SIInstrInfo &TII) { in getRegs() argument
429 if (TII.isMUBUF(Opc)) { in getRegs()
440 if (TII.isMIMG(Opc)) { in getRegs()
455 if (TII.isMTBUF(Opc)) { in getRegs()
488 const SIInstrInfo &TII, in setMI() argument
492 InstClass = getInstClass(Opc, TII); in setMI()
517 DMask = TII.getNamedOperand(*I, AMDGPU::OpName::dmask)->getImm(); in setMI()
526 Format = TII.getNamedOperand(*I, AMDGPU::OpName::format)->getImm(); in setMI()
528 Width = getOpcodeWidth(*I, TII); in setMI()
533 CPol = TII.getNamedOperand(*I, AMDGPU::OpName::cpol)->getImm(); in setMI()
536 AddressRegs Regs = getRegs(Opc, TII); in setMI()
671 const SIInstrInfo &TII, in dmasksCanBeCombined() argument
676 const auto *TFEOp = TII.getNamedOperand(*CI.I, AMDGPU::OpName::tfe); in dmasksCanBeCombined()
677 const auto *LWEOp = TII.getNamedOperand(*CI.I, AMDGPU::OpName::lwe); in dmasksCanBeCombined()
873 if (const auto *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst)) { in getDataRegClass()
876 if (const auto *Src = TII->getNamedOperand(MI, AMDGPU::OpName::vdata)) { in getDataRegClass()
879 if (const auto *Src = TII->getNamedOperand(MI, AMDGPU::OpName::data0)) { in getDataRegClass()
882 if (const auto *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst)) { in getDataRegClass()
885 if (const auto *Src = TII->getNamedOperand(MI, AMDGPU::OpName::sdata)) { in getDataRegClass()
898 if (CI.InstClass == MIMG && !dmasksCanBeCombined(CI, *TII, Paired)) in checkAndPrepareMerge()
906 const InstClassEnum InstClass = getInstClass(Opc, *TII); in checkAndPrepareMerge()
911 const unsigned InstSubclass = getInstSubclass(Opc, *TII); in checkAndPrepareMerge()
941 if ((getInstClass(MBBI->getOpcode(), *TII) != InstClass) || in checkAndPrepareMerge()
942 (getInstSubclass(MBBI->getOpcode(), *TII) != InstSubclass)) { in checkAndPrepareMerge()
1054 const auto *AddrReg = TII->getNamedOperand(*CI.I, AMDGPU::OpName::addr); in mergeRead2Pair()
1056 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdst); in mergeRead2Pair()
1057 const auto *Dest1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdst); in mergeRead2Pair()
1076 const MCInstrDesc &Read2Desc = TII->get(Opc); in mergeRead2Pair()
1088 BuildMI(*MBB, Paired.I, DL, TII->get(AMDGPU::S_MOV_B32), ImmReg) in mergeRead2Pair()
1094 TII->getAddNoCarry(*MBB, Paired.I, DL, BaseReg) in mergeRead2Pair()
1111 const MCInstrDesc &CopyDesc = TII->get(TargetOpcode::COPY); in mergeRead2Pair()
1154 TII->getNamedOperand(*CI.I, AMDGPU::OpName::addr); in mergeWrite2Pair()
1156 TII->getNamedOperand(*CI.I, AMDGPU::OpName::data0); in mergeWrite2Pair()
1158 TII->getNamedOperand(*Paired.I, AMDGPU::OpName::data0); in mergeWrite2Pair()
1174 const MCInstrDesc &Write2Desc = TII->get(Opc); in mergeWrite2Pair()
1182 BuildMI(*MBB, Paired.I, DL, TII->get(AMDGPU::S_MOV_B32), ImmReg) in mergeWrite2Pair()
1188 TII->getAddNoCarry(*MBB, Paired.I, DL, BaseReg) in mergeWrite2Pair()
1228 auto MIB = BuildMI(*MBB, Paired.I, DL, TII->get(Opcode), DestReg); in mergeImagePair()
1250 const MCInstrDesc &CopyDesc = TII->get(TargetOpcode::COPY); in mergeImagePair()
1251 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); in mergeImagePair()
1252 const auto *Dest1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdata); in mergeImagePair()
1289 BuildMI(*MBB, Paired.I, DL, TII->get(Opcode), DestReg) in mergeSBufferLoadImmPair()
1290 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::sbase)) in mergeSBufferLoadImmPair()
1300 const MCInstrDesc &CopyDesc = TII->get(TargetOpcode::COPY); in mergeSBufferLoadImmPair()
1301 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::sdst); in mergeSBufferLoadImmPair()
1302 const auto *Dest1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::sdst); in mergeSBufferLoadImmPair()
1332 auto MIB = BuildMI(*MBB, Paired.I, DL, TII->get(Opcode), DestReg); in mergeBufferLoadPair()
1334 AddressRegs Regs = getRegs(Opcode, *TII); in mergeBufferLoadPair()
1337 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr)); in mergeBufferLoadPair()
1348 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc)) in mergeBufferLoadPair()
1349 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset)) in mergeBufferLoadPair()
1361 const MCInstrDesc &CopyDesc = TII->get(TargetOpcode::COPY); in mergeBufferLoadPair()
1362 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); in mergeBufferLoadPair()
1363 const auto *Dest1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdata); in mergeBufferLoadPair()
1393 auto MIB = BuildMI(*MBB, Paired.I, DL, TII->get(Opcode), DestReg); in mergeTBufferLoadPair()
1395 AddressRegs Regs = getRegs(Opcode, *TII); in mergeTBufferLoadPair()
1398 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr)); in mergeTBufferLoadPair()
1412 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc)) in mergeTBufferLoadPair()
1413 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset)) in mergeTBufferLoadPair()
1427 const MCInstrDesc &CopyDesc = TII->get(TargetOpcode::COPY); in mergeTBufferLoadPair()
1428 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); in mergeTBufferLoadPair()
1429 const auto *Dest1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdata); in mergeTBufferLoadPair()
1461 const auto *Src0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); in mergeTBufferStorePair()
1462 const auto *Src1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdata); in mergeTBufferStorePair()
1464 BuildMI(*MBB, Paired.I, DL, TII->get(AMDGPU::REG_SEQUENCE), SrcReg) in mergeTBufferStorePair()
1470 auto MIB = BuildMI(*MBB, Paired.I, DL, TII->get(Opcode)) in mergeTBufferStorePair()
1473 AddressRegs Regs = getRegs(Opcode, *TII); in mergeTBufferStorePair()
1476 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr)); in mergeTBufferStorePair()
1490 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc)) in mergeTBufferStorePair()
1491 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset)) in mergeTBufferStorePair()
1616 const auto *Src0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); in mergeBufferStorePair()
1617 const auto *Src1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdata); in mergeBufferStorePair()
1619 BuildMI(*MBB, Paired.I, DL, TII->get(AMDGPU::REG_SEQUENCE), SrcReg) in mergeBufferStorePair()
1625 auto MIB = BuildMI(*MBB, Paired.I, DL, TII->get(Opcode)) in mergeBufferStorePair()
1628 AddressRegs Regs = getRegs(Opcode, *TII); in mergeBufferStorePair()
1631 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr)); in mergeBufferStorePair()
1643 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc)) in mergeBufferStorePair()
1644 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset)) in mergeBufferStorePair()
1661 if (TII->isInlineConstant(V)) in createRegOrImm()
1667 TII->get(AMDGPU::S_MOV_B32), Reg) in createRegOrImm()
1701 BuildMI(*MBB, MBBI, DL, TII->get(AMDGPU::V_ADD_CO_U32_e64), DestSub0) in computeBase()
1710 BuildMI(*MBB, MBBI, DL, TII->get(AMDGPU::V_ADDC_U32_e64), DestSub1) in computeBase()
1721 BuildMI(*MBB, MBBI, DL, TII->get(TargetOpcode::REG_SEQUENCE), FullDestReg) in computeBase()
1736 auto Base = TII->getNamedOperand(MI, AMDGPU::OpName::vaddr); in updateBaseAndOffset()
1739 TII->getNamedOperand(MI, AMDGPU::OpName::offset)->setImm(NewOffset); in updateBaseAndOffset()
1790 const auto *Src0 = TII->getNamedOperand(*BaseLoDef, AMDGPU::OpName::src0); in processBaseWithConstOffset()
1791 const auto *Src1 = TII->getNamedOperand(*BaseLoDef, AMDGPU::OpName::src1); in processBaseWithConstOffset()
1802 Src0 = TII->getNamedOperand(*BaseHiDef, AMDGPU::OpName::src0); in processBaseWithConstOffset()
1803 Src1 = TII->getNamedOperand(*BaseHiDef, AMDGPU::OpName::src1); in processBaseWithConstOffset()
1833 if (MI.mayLoad() && TII->getNamedOperand(MI, AMDGPU::OpName::vdata) != NULL) in promoteConstantOffsetToImm()
1841 if (TII->getNamedOperand(MI, AMDGPU::OpName::offset)->getImm()) { in promoteConstantOffsetToImm()
1847 MachineOperand &Base = *TII->getNamedOperand(MI, AMDGPU::OpName::vaddr); in promoteConstantOffsetToImm()
1906 TII->getNamedOperand(MINext, AMDGPU::OpName::offset)->getImm()) in promoteConstantOffsetToImm()
1910 *TII->getNamedOperand(MINext, AMDGPU::OpName::vaddr); in promoteConstantOffsetToImm()
2012 const InstClassEnum InstClass = getInstClass(MI.getOpcode(), *TII); in collectMergeableInsts()
2017 CI.setMI(MI, *TII, *STM); in collectMergeableInsts()
2130 CI.setMI(NewMI, *TII, *STM); in optimizeInstsWithSameBaseAddr()
2136 CI.setMI(NewMI, *TII, *STM); in optimizeInstsWithSameBaseAddr()
2142 CI.setMI(NewMI, *TII, *STM); in optimizeInstsWithSameBaseAddr()
2149 CI.setMI(NewMI, *TII, *STM); in optimizeInstsWithSameBaseAddr()
2156 CI.setMI(NewMI, *TII, *STM); in optimizeInstsWithSameBaseAddr()
2163 CI.setMI(NewMI, *TII, *STM); in optimizeInstsWithSameBaseAddr()
2170 CI.setMI(NewMI, *TII, *STM); in optimizeInstsWithSameBaseAddr()
2177 CI.setMI(NewMI, *TII, *STM); in optimizeInstsWithSameBaseAddr()
2200 TII = STM->getInstrInfo(); in runOnMachineFunction()
2201 TRI = &TII->getRegisterInfo(); in runOnMachineFunction()