Lines Matching refs:TII
82 const SIInstrInfo *TII; member in __anon3d458c240111::SIFoldOperands
151 static bool isInlineConstantIfFolded(const SIInstrInfo *TII, in isInlineConstantIfFolded() argument
155 if (TII->isInlineConstant(UseMI, OpNo, OpToFold)) in isInlineConstantIfFolded()
165 const MCInstrDesc &MadDesc = TII->get(NewOpc); in isInlineConstantIfFolded()
166 return TII->isInlineConstant(OpToFold, MadDesc.OpInfo[OpNo].OperandType); in isInlineConstantIfFolded()
175 static bool frameIndexMayFold(const SIInstrInfo *TII, in frameIndexMayFold() argument
182 if (TII->isMUBUF(UseMI)) in frameIndexMayFold()
185 if (!TII->isFLATScratch(UseMI)) in frameIndexMayFold()
203 const SIInstrInfo &TII, in updateOperand() argument
233 switch (TII.get(Opcode).OpInfo[OpNo].OperandType) { in updateOperand()
277 MachineInstr *Inst32 = TII.buildShrunkInst(*MI, Op32); in updateOperand()
280 BuildMI(*MBB, MI, MI->getDebugLoc(), TII.get(AMDGPU::COPY), Dst1.getReg()) in updateOperand()
293 MI->setDesc(TII.get(AMDGPU::IMPLICIT_DEF)); in updateOperand()
296 TII.commuteInstruction(*Inst32, false); in updateOperand()
349 const SIInstrInfo *TII) { in tryAddToFoldList() argument
350 if (!TII->isOperandLegal(*MI, OpNo, OpToFold)) { in tryAddToFoldList()
357 MI->setDesc(TII->get(NewOpc)); in tryAddToFoldList()
358 bool FoldAsMAD = tryAddToFoldList(FoldList, MI, OpNo, OpToFold, TII); in tryAddToFoldList()
363 MI->setDesc(TII->get(Opc)); in tryAddToFoldList()
374 MI->setDesc(TII->get(ImmOpc)); in tryAddToFoldList()
392 bool CanCommute = TII->findCommutedOpIndices(*MI, CommuteIdx0, CommuteIdx1); in tryAddToFoldList()
411 !TII->commuteInstruction(*MI, false, CommuteIdx0, CommuteIdx1)) in tryAddToFoldList()
414 if (!TII->isOperandLegal(*MI, CommuteOpNo, OpToFold)) { in tryAddToFoldList()
426 !TII->getRegisterInfo().isVGPR(MRI, OtherOp.getReg())) in tryAddToFoldList()
439 TII->commuteInstruction(*MI, false, CommuteIdx0, CommuteIdx1); in tryAddToFoldList()
449 if (TII->isSALU(MI->getOpcode())) { in tryAddToFoldList()
452 const SIRegisterInfo &SRI = TII->getRegisterInfo(); in tryAddToFoldList()
457 !TII->isInlineConstant(*OpToFold, OpInfo)) { in tryAddToFoldList()
462 TII->isLiteralConstantLike(Op, OpInfo)) { in tryAddToFoldList()
476 static bool isUseSafeToFold(const SIInstrInfo *TII, in isUseSafeToFold() argument
479 if (UseMO.isUndef() || TII->isSDWA(MI)) in isUseSafeToFold()
500 const SIInstrInfo *TII, const MachineRegisterInfo &MRI) { in getRegSeqInit() argument
511 !Sub->getSubReg() && TII->isFoldableCopy(*SubDef); in getRegSeqInit()
515 if (TII->isInlineConstant(*Op, OpTy)) in getRegSeqInit()
530 static bool tryToFoldACImm(const SIInstrInfo *TII, in tryToFoldACImm() argument
547 if (OpToFold.isImm() && TII->isInlineConstant(OpToFold, OpTy) && in tryToFoldACImm()
548 TII->isOperandLegal(*UseMI, UseOpIdx, &OpToFold)) { in tryToFoldACImm()
568 if (!UseOp.getSubReg() && Def && TII->isFoldableCopy(*Def)) { in tryToFoldACImm()
570 if (DefOp.isImm() && TII->isInlineConstant(DefOp, OpTy) && in tryToFoldACImm()
571 TII->isOperandLegal(*UseMI, UseOpIdx, &DefOp)) { in tryToFoldACImm()
578 if (!getRegSeqInit(Defs, UseReg, OpTy, TII, MRI)) in tryToFoldACImm()
590 if (!TII->isInlineConstant(*Op, OpTy) || in tryToFoldACImm()
591 !TII->isOperandLegal(*UseMI, UseOpIdx, Op)) in tryToFoldACImm()
612 if (!isUseSafeToFold(TII, *UseMI, UseOp)) in foldOperand()
631 if (tryToFoldACImm(TII, UseMI->getOperand(0), RSUseMI, in foldOperand()
645 if (tryToFoldACImm(TII, OpToFold, UseMI, UseOpIdx, FoldList)) in foldOperand()
648 if (frameIndexMayFold(TII, *UseMI, UseOpIdx, OpToFold)) { in foldOperand()
652 if (TII->isMUBUF(*UseMI)) { in foldOperand()
653 if (TII->getNamedOperand(*UseMI, AMDGPU::OpName::srsrc)->getReg() != in foldOperand()
660 *TII->getNamedOperand(*UseMI, AMDGPU::OpName::soffset); in foldOperand()
669 if (TII->isFLATScratch(*UseMI) && in foldOperand()
673 UseMI->setDesc(TII->get(NewOpc)); in foldOperand()
714 TII->isInlineConstant(OpToFold, AMDGPU::OPERAND_REG_INLINE_C_INT32)) { in foldOperand()
715 UseMI->setDesc(TII->get(AMDGPU::V_ACCVGPR_WRITE_B32_e64)); in foldOperand()
725 unsigned MovOp = TII->getMovOpcode(DestRC); in foldOperand()
729 UseMI->setDesc(TII->get(MovOp)); in foldOperand()
743 unsigned Size = TII->getOpSize(*UseMI, 1); in foldOperand()
757 getRegSeqInit(Defs, UseReg, AMDGPU::OPERAND_REG_INLINE_C_INT32, TII, in foldOperand()
762 UseMI->setDesc(TII->get(AMDGPU::REG_SEQUENCE)); in foldOperand()
773 TII->isInlineConstant(*Def, AMDGPU::OPERAND_REG_INLINE_C_INT32)) { in foldOperand()
778 TII->get(AMDGPU::V_ACCVGPR_WRITE_B32_e64), Tmp).addImm(Imm); in foldOperand()
804 BuildMI(MBB, UseMI, DL, TII->get(AMDGPU::COPY), Tmp).add(*Def); in foldOperand()
815 BuildMI(MBB, UseMI, DL, TII->get(AMDGPU::COPY), Vgpr).add(*Def); in foldOperand()
820 TII->get(AMDGPU::V_ACCVGPR_WRITE_B32_e64), Tmp).addReg(Vgpr); in foldOperand()
834 UseMI->setDesc(TII->get(AMDGPU::V_ACCVGPR_WRITE_B32_e64)); in foldOperand()
837 UseMI->setDesc(TII->get(AMDGPU::V_ACCVGPR_READ_B32_e64)); in foldOperand()
841 UseMI->setDesc(TII->get(AMDGPU::V_ACCVGPR_MOV_B32)); in foldOperand()
861 UseMI->setDesc(TII->get(AMDGPU::S_MOV_B32)); in foldOperand()
882 UseMI->setDesc(TII->get(AMDGPU::COPY)); in foldOperand()
902 tryAddToFoldList(FoldList, UseMI, UseOpIdx, &OpToFold, TII); in foldOperand()
932 tryAddToFoldList(FoldList, UseMI, UseOpIdx, &ImmOp, TII); in foldOperand()
938 tryAddToFoldList(FoldList, UseMI, UseOpIdx, &OpToFold, TII); in foldOperand()
1050 static bool tryConstantFoldOp(MachineRegisterInfo &MRI, const SIInstrInfo *TII, in tryConstantFoldOp() argument
1063 mutateCopyOp(*MI, TII->get(getMovOpc(Opc == AMDGPU::S_NOT_B32))); in tryConstantFoldOp()
1083 const SIRegisterInfo &TRI = TII->getRegisterInfo(); in tryConstantFoldOp()
1090 mutateCopyOp(*MI, TII->get(getMovOpc(IsSGPR))); in tryConstantFoldOp()
1109 mutateCopyOp(*MI, TII->get(AMDGPU::COPY)); in tryConstantFoldOp()
1113 mutateCopyOp(*MI, TII->get(getMovOpc(Opc == AMDGPU::S_OR_B32))); in tryConstantFoldOp()
1126 mutateCopyOp(*MI, TII->get(getMovOpc(Opc == AMDGPU::S_AND_B32))); in tryConstantFoldOp()
1130 mutateCopyOp(*MI, TII->get(AMDGPU::COPY)); in tryConstantFoldOp()
1144 mutateCopyOp(*MI, TII->get(AMDGPU::COPY)); in tryConstantFoldOp()
1159 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in tryFoldCndMask()
1160 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in tryFoldCndMask()
1178 TII->get(Src0->isReg() ? (unsigned)AMDGPU::COPY : getMovOpc(false)); in tryFoldCndMask()
1233 if (tryConstantFoldOp(*MRI, TII, &UseMI)) in foldInstOperand()
1264 if (isInlineConstantIfFolded(TII, *UseMI, OpNo, OpToFold)) { in foldInstOperand()
1266 } else if (frameIndexMayFold(TII, *UseMI, OpNo, OpToFold)) { in foldInstOperand()
1307 if (updateOperand(Fold, *TII, *TRI, *ST)) { in foldInstOperand()
1321 TII->commuteInstruction(*Fold.UseMI, false); in foldInstOperand()
1335 if (!TII->getNamedOperand(MI, AMDGPU::OpName::clamp)->getImm()) in isClamp()
1339 const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in isClamp()
1340 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in isClamp()
1348 if (TII->hasModifiersSet(MI, AMDGPU::OpName::omod)) in isClamp()
1352 = TII->getNamedOperand(MI, AMDGPU::OpName::src0_modifiers)->getImm(); in isClamp()
1354 = TII->getNamedOperand(MI, AMDGPU::OpName::src1_modifiers)->getImm(); in isClamp()
1378 if (TII->getClampMask(*Def) != TII->getClampMask(MI)) in tryFoldClamp()
1381 MachineOperand *DefClamp = TII->getNamedOperand(*Def, AMDGPU::OpName::clamp); in tryFoldClamp()
1455 const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in isOMod()
1456 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in isOMod()
1468 TII->hasModifiersSet(MI, AMDGPU::OpName::src0_modifiers) || in isOMod()
1469 TII->hasModifiersSet(MI, AMDGPU::OpName::src1_modifiers) || in isOMod()
1470 TII->hasModifiersSet(MI, AMDGPU::OpName::omod) || in isOMod()
1471 TII->hasModifiersSet(MI, AMDGPU::OpName::clamp)) in isOMod()
1486 const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in isOMod()
1487 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in isOMod()
1491 !TII->hasModifiersSet(MI, AMDGPU::OpName::src0_modifiers) && in isOMod()
1492 !TII->hasModifiersSet(MI, AMDGPU::OpName::src1_modifiers) && in isOMod()
1493 !TII->hasModifiersSet(MI, AMDGPU::OpName::clamp) && in isOMod()
1494 !TII->hasModifiersSet(MI, AMDGPU::OpName::omod)) in isOMod()
1515 MachineOperand *DefOMod = TII->getNamedOperand(*Def, AMDGPU::OpName::omod); in tryFoldOMod()
1521 if (TII->hasModifiersSet(*Def, AMDGPU::OpName::clamp)) in tryFoldOMod()
1543 if (!getRegSeqInit(Defs, Reg, MCOI::OPERAND_REGISTER, TII, *MRI)) in tryFoldRegSequence()
1590 TII->get(AMDGPU::REG_SEQUENCE), Dst); in tryFoldRegSequence()
1606 if (!TII->isOperandLegal(*UseMI, OpIdx, Op)) { in tryFoldRegSequence()
1661 TII->get(AMDGPU::COPY), PhiOut) in tryFoldLCSSAPhi()
1709 if (!TII->isOperandLegal(MI, 0, &Def)) { in tryFoldLoad()
1730 TII = ST->getInstrInfo(); in runOnMachineFunction()
1731 TRI = &TII->getRegisterInfo(); in runOnMachineFunction()
1758 if (!TII->isFoldableCopy(MI)) { in runOnMachineFunction()
1823 if (!InstToErase || !TII->isFoldableCopy(*InstToErase)) in runOnMachineFunction()