Lines Matching refs:TII
277 const DebugLoc &dl, const ARMBaseInstrInfo &TII, unsigned DestReg, in emitRegPlusImmediate() argument
282 Pred, PredReg, TII, MIFlags); in emitRegPlusImmediate()
285 Pred, PredReg, TII, MIFlags); in emitRegPlusImmediate()
290 const ARMBaseInstrInfo &TII, int NumBytes, in emitSPUpdate() argument
294 emitRegPlusImmediate(isARM, MBB, MBBI, dl, TII, ARM::SP, ARM::SP, NumBytes, in emitSPUpdate()
361 const ARMBaseInstrInfo &TII, bool HasFP) { in emitDefCFAOffsets()
372 TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitDefCFAOffsets()
389 const TargetInstrInfo &TII, in emitAligningInstructions() argument
412 BuildMI(MBB, MBBI, DL, TII.get(ARM::BFC), Reg) in emitAligningInstructions()
417 BuildMI(MBB, MBBI, DL, TII.get(ARM::BICri), Reg) in emitAligningInstructions()
427 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg) in emitAligningInstructions()
432 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg) in emitAligningInstructions()
442 BuildMI(MBB, MBBI, DL, TII.get(ARM::t2BFC), Reg) in emitAligningInstructions()
476 const ARMBaseInstrInfo &TII = *STI.getInstrInfo(); in emitPrologue() local
508 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -ArgRegsSaveSize, in emitPrologue()
516 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -(NumBytes - ArgRegsSaveSize), in emitPrologue()
521 DefCFAOffsetCandidates.emitDefCFAOffsets(MBB, dl, TII, HasFP); in emitPrologue()
615 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRGapSize, in emitPrologue()
646 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4) in emitPrologue()
651 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R4) in emitPrologue()
661 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBL)) in emitPrologue()
668 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R12) in emitPrologue()
672 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBLXr)) in emitPrologue()
680 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), ARM::SP) in emitPrologue()
695 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes, in emitPrologue()
722 dl, TII, FramePtr, ARM::SP, in emitPrologue()
729 BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
736 BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
771 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
795 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
817 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
828 DefCFAOffsetCandidates.emitDefCFAOffsets(MBB, dl, TII, HasFP); in emitPrologue()
848 emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::SP, MaxAlign, in emitPrologue()
858 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4) in emitPrologue()
861 emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::R4, MaxAlign, in emitPrologue()
863 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP) in emitPrologue()
878 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), RegInfo->getBaseRegister()) in emitPrologue()
883 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), RegInfo->getBaseRegister()) in emitPrologue()
900 const ARMBaseInstrInfo &TII = in emitEpilogue() local
927 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes - ReservedArgStack, in emitEpilogue()
955 ARMCC::AL, 0, TII, in emitEpilogue()
968 ARMCC::AL, 0, TII, MachineInstr::FrameDestroy); in emitEpilogue()
969 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP) in emitEpilogue()
977 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP) in emitEpilogue()
983 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP) in emitEpilogue()
990 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes, in emitEpilogue()
1004 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedGapSize(), in emitEpilogue()
1016 emitSPUpdate(isARM, MBB, MBBI, dl, TII, in emitEpilogue()
1122 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); in emitPushInst() local
1167 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP) in emitPushInst()
1174 BuildMI(MBB, MI, DL, TII.get(StrOpc), ARM::SP) in emitPushInst()
1199 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); in emitPopInst() local
1262 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP) in emitPopInst()
1281 BuildMI(MBB, MI, DL, TII.get(LdrOpc), Regs[0]) in emitPopInst()
1314 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); in emitAlignedDPRCS2Spills() local
1353 BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4) in emitAlignedDPRCS2Spills()
1365 emitAligningInstructions(MF, AFI, TII, MBB, MI, DL, ARM::R4, MaxAlign, true); in emitAlignedDPRCS2Spills()
1372 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP) in emitAlignedDPRCS2Spills()
1388 BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Qwb_fixed), ARM::R4) in emitAlignedDPRCS2Spills()
1407 BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Q)) in emitAlignedDPRCS2Spills()
1422 BuildMI(MBB, MI, DL, TII.get(ARM::VST1q64)) in emitAlignedDPRCS2Spills()
1435 BuildMI(MBB, MI, DL, TII.get(ARM::VSTRD)) in emitAlignedDPRCS2Spills()
1487 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); in emitAlignedDPRCS2Restores() local
1506 BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4) in emitAlignedDPRCS2Restores()
1519 BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Qwb_fixed), NextReg) in emitAlignedDPRCS2Restores()
1537 BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Q), NextReg) in emitAlignedDPRCS2Restores()
1550 BuildMI(MBB, MI, DL, TII.get(ARM::VLD1q64), SupReg) in emitAlignedDPRCS2Restores()
1560 BuildMI(MBB, MI, DL, TII.get(ARM::VLDRD), NextReg) in emitAlignedDPRCS2Restores()
1640 const ARMBaseInstrInfo &TII) { in EstimateFunctionSizeInBytes() argument
1644 FnSize += TII.getInstSizeInBytes(MI); in EstimateFunctionSizeInBytes()
1661 const ARMBaseInstrInfo &TII = in estimateRSStackSizeLimit() local
1685 const TargetRegisterClass *RegClass = TII.getRegClass(MCID, i, TRI, MF); in estimateRSStackSizeLimit()
1812 const ARMBaseInstrInfo &TII = in determineCalleeSaves() local
1938 unsigned FnSize = EstimateFunctionSizeInBytes(MF, TII); in determineCalleeSaves()
2331 const ARMBaseInstrInfo &TII = in eliminateCallFramePseudoInstr() local
2337 bool IsDestroy = Opc == TII.getCallFrameDestroyOpcode(); in eliminateCallFramePseudoInstr()
2347 unsigned PredReg = TII.getFramePred(*I); in eliminateCallFramePseudoInstr()
2357 unsigned Amount = TII.getFrameSize(*I); in eliminateCallFramePseudoInstr()
2365 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, MachineInstr::NoFlags, in eliminateCallFramePseudoInstr()
2369 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, MachineInstr::NoFlags, in eliminateCallFramePseudoInstr()
2376 emitSPUpdate(isARM, MBB, I, dl, TII, -CalleePopAmount, in eliminateCallFramePseudoInstr()
2457 const ARMBaseInstrInfo &TII = in adjustForSegmentedStacks() local
2546 BuildMI(PrevStackMBB, DL, TII.get(ARM::tPUSH)) in adjustForSegmentedStacks()
2551 BuildMI(PrevStackMBB, DL, TII.get(ARM::STMDB_UPD)) in adjustForSegmentedStacks()
2562 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) in adjustForSegmentedStacks()
2566 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) in adjustForSegmentedStacks()
2570 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) in adjustForSegmentedStacks()
2575 BuildMI(McrMBB, DL, TII.get(ARM::tMOVr), ScratchReg1) in adjustForSegmentedStacks()
2579 BuildMI(McrMBB, DL, TII.get(ARM::MOVr), ScratchReg1) in adjustForSegmentedStacks()
2587 BuildMI(McrMBB, DL, TII.get(ARM::tSUBi8), ScratchReg1) in adjustForSegmentedStacks()
2593 BuildMI(McrMBB, DL, TII.get(ARM::SUBri), ScratchReg1) in adjustForSegmentedStacks()
2608 BuildMI(GetMBB, DL, TII.get(ARM::tLDRpci), ScratchReg0) in adjustForSegmentedStacks()
2613 BuildMI(GetMBB, DL, TII.get(ARM::tLDRi), ScratchReg0) in adjustForSegmentedStacks()
2620 BuildMI(McrMBB, DL, TII.get(Thumb ? ARM::t2MRC : ARM::MRC), in adjustForSegmentedStacks()
2635 BuildMI(GetMBB, DL, TII.get(Thumb ? ARM::t2LDRi12 : ARM::LDRi12), in adjustForSegmentedStacks()
2645 BuildMI(GetMBB, DL, TII.get(Opcode)) in adjustForSegmentedStacks()
2652 BuildMI(GetMBB, DL, TII.get(Opcode)).addMBB(PostStackMBB) in adjustForSegmentedStacks()
2664 BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ScratchReg0) in adjustForSegmentedStacks()
2669 BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg0) in adjustForSegmentedStacks()
2677 BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ScratchReg1) in adjustForSegmentedStacks()
2682 BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg1) in adjustForSegmentedStacks()
2690 BuildMI(AllocMBB, DL, TII.get(ARM::tPUSH)) in adjustForSegmentedStacks()
2694 BuildMI(AllocMBB, DL, TII.get(ARM::STMDB_UPD)) in adjustForSegmentedStacks()
2704 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) in adjustForSegmentedStacks()
2708 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) in adjustForSegmentedStacks()
2713 BuildMI(AllocMBB, DL, TII.get(ARM::tBL)) in adjustForSegmentedStacks()
2717 BuildMI(AllocMBB, DL, TII.get(ARM::BL)) in adjustForSegmentedStacks()
2724 BuildMI(AllocMBB, DL, TII.get(ARM::tPOP)) in adjustForSegmentedStacks()
2727 BuildMI(AllocMBB, DL, TII.get(ARM::tMOVr), ARM::LR) in adjustForSegmentedStacks()
2731 BuildMI(AllocMBB, DL, TII.get(ARM::t2LDR_POST)) in adjustForSegmentedStacks()
2739 BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD)) in adjustForSegmentedStacks()
2751 BuildMI(AllocMBB, DL, TII.get(ARM::tPOP)) in adjustForSegmentedStacks()
2756 BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD)) in adjustForSegmentedStacks()
2766 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) in adjustForSegmentedStacks()
2770 BuildMI(AllocMBB, DL, TII.get(ST->getReturnOpcode())).add(predOps(ARMCC::AL)); in adjustForSegmentedStacks()
2775 BuildMI(PostStackMBB, DL, TII.get(ARM::tPOP)) in adjustForSegmentedStacks()
2780 BuildMI(PostStackMBB, DL, TII.get(ARM::LDMIA_UPD)) in adjustForSegmentedStacks()
2790 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) in adjustForSegmentedStacks()
2797 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) in adjustForSegmentedStacks()
2801 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) in adjustForSegmentedStacks()