56   const SIInstrInfo *TII;  member in __anonb4df09800111::GCNDPPCombine
119   if (!TII->isVOP3(Op)) {  in isShrinkable()
122   if (!TII->hasVALU32BitEncoding(Op)) {  in isShrinkable()
126   if (const auto *SDst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst)) {  in isShrinkable()
152   return (DPP32 == -1 || TII->pseudoToMCOpcode(DPP32) == -1) ? -1 : DPP32;  in getDPPOp()
196                          OrigMI.getDebugLoc(), TII->get(DPPOp))  in createDPPInst()
201     auto *Dst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst);  in createDPPInst()
212               TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst)->getReg()),  in createDPPInst()
226     if (auto *Mod0 = TII->getNamedOperand(OrigMI,  in createDPPInst()
238     auto *Src0 = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0);  in createDPPInst()
240     if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src0)) {  in createDPPInst()
249     if (auto *Mod1 = TII->getNamedOperand(OrigMI,  in createDPPInst()
261     if (auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1)) {  in createDPPInst()
262       if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src1)) {  in createDPPInst()
271     if (auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2)) {  in createDPPInst()
272       if (!TII->getNamedOperand(*DPPInst.getInstr(), AMDGPU::OpName::src2) ||  in createDPPInst()
273           !TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src2)) {  in createDPPInst()
281     DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::dpp_ctrl));  in createDPPInst()
282     DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask));  in createDPPInst()
283     DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::bank_mask));  in createDPPInst()
352     auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1);  in createDPPInst()
362     auto MovDst = TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst);  in createDPPInst()
376   auto *Imm = TII->getNamedOperand(MI, OpndName);  in hasNoImmOrEqual()
389   auto *DstOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst);  in combineDPPMov()
403     auto *DppCtrl = TII->getNamedOperand(MovMI, AMDGPU::OpName::dpp_ctrl);  in combineDPPMov()
413   auto *RowMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask);  in combineDPPMov()
415   auto *BankMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::bank_mask);  in combineDPPMov()
420   auto *BCZOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::bound_ctrl);  in combineDPPMov()
424   auto *OldOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::old);  in combineDPPMov()
425   auto *SrcOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0);  in combineDPPMov()
485                              TII->get(AMDGPU::IMPLICIT_DEF), CombOldVGPR.Reg);  in combineDPPMov()
535     if (!(IsShrinkable || TII->isVOP1(OrigOp) || TII->isVOP2(OrigOp))) {  in combineDPPMov()
540     auto *Src0 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src0);  in combineDPPMov()
541     auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1);  in combineDPPMov()
569       if (TII->commuteInstruction(*NewMI)) {  in combineDPPMov()
611   TII = ST->getInstrInfo();  in runOnMachineFunction()
625           auto Split = TII->expandMovDPP64(MI);  in runOnMachineFunction()