Lines Matching refs:TII

137   void processBlockPhase1(MachineBasicBlock &MBB, const SIInstrInfo *TII);
139 void processBlockPhase2(MachineBasicBlock &MBB, const SIInstrInfo *TII);
141 void processBlockPhase3(MachineBasicBlock &MBB, const SIInstrInfo *TII);
143 Status getInstructionMode(MachineInstr &MI, const SIInstrInfo *TII);
146 const SIInstrInfo *TII, Status InstrMode);
164 const SIInstrInfo *TII) { in getInstructionMode() argument
165 if (TII->usesFPDPRounding(MI)) { in getInstructionMode()
186 const SIInstrInfo *TII, Status InstrMode) { in insertSetreg() argument
191 BuildMI(MBB, MI, 0, TII->get(AMDGPU::S_SETREG_IMM32_B32)) in insertSetreg()
222 const SIInstrInfo *TII) { in processBlockPhase1() argument
233 Status InstrMode = getInstructionMode(MI, TII); in processBlockPhase1()
241 unsigned Dst = TII->getNamedOperand(MI, AMDGPU::OpName::simm16)->getImm(); in processBlockPhase1()
255 insertSetreg(MBB, InsertionPoint, TII, IPChange.delta(NewInfo->Change)); in processBlockPhase1()
263 unsigned Val = TII->getNamedOperand(MI, AMDGPU::OpName::imm)->getImm(); in processBlockPhase1()
289 insertSetreg(MBB, InsertionPoint, TII, in processBlockPhase1()
313 insertSetreg(MBB, InsertionPoint, TII, IPChange.delta(NewInfo->Change)); in processBlockPhase1()
324 const SIInstrInfo *TII) { in processBlockPhase2() argument
392 const SIInstrInfo *TII) { in processBlockPhase3() argument
398 insertSetreg(MBB, BlockInfo[ThisBlock]->FirstInsertionPoint, TII, Delta); in processBlockPhase3()
400 insertSetreg(MBB, &MBB.instr_front(), TII, Delta); in processBlockPhase3()
407 const SIInstrInfo *TII = ST.getInstrInfo(); in runOnMachineFunction() local
414 processBlockPhase1(BB, TII); in runOnMachineFunction()
422 processBlockPhase2(*Phase2List.front(), TII); in runOnMachineFunction()
429 processBlockPhase3(BB, TII); in runOnMachineFunction()