| /freebsd-12.1/contrib/llvm/tools/clang/lib/StaticAnalyzer/Core/ |
| H A D | SimpleConstraintManager.cpp | 27 DefinedSVal Cond, in assume() argument
30 if (Optional<Loc> LV = Cond.getAs<Loc>()) { in assume()
42 return assume(State, Cond.castAs<NonLoc>(), Assumption); in assume()
47 State = assumeAux(State, Cond, Assumption); in assume()
49 return SU->processAssume(State, Cond, Assumption); in assume()
54 NonLoc Cond, in assumeAux() argument
59 if (!canReasonAbout(Cond)) { in assumeAux()
61 SymbolRef Sym = Cond.getAsSymExpr(); in assumeAux()
66 switch (Cond.getSubKind()) { in assumeAux()
71 nonloc::SymbolVal SV = Cond.castAs<nonloc::SymbolVal>(); in assumeAux()
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| /freebsd-12.1/contrib/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyInstrInfo.cpp | 113 Cond.push_back(MachineOperand::CreateImm(true)); in analyzeBranch()
114 Cond.push_back(MI.getOperand(1)); in analyzeBranch()
124 Cond.push_back(MachineOperand::CreateImm(false)); in analyzeBranch()
125 Cond.push_back(MI.getOperand(1)); in analyzeBranch()
173 if (Cond.empty()) { in insertBranch()
181 assert(Cond.size() == 2 && "Expected a flag and a successor block"); in insertBranch()
183 if (Cond[0].getImm()) { in insertBranch()
184 BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addMBB(TBB).add(Cond[1]); in insertBranch()
196 SmallVectorImpl<MachineOperand> &Cond) const { in reverseBranchCondition()
197 assert(Cond.size() == 2 && "Expected a flag and a successor block"); in reverseBranchCondition()
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| H A D | WebAssemblyLowerBrUnless.cpp | 72 unsigned Cond = MI->getOperand(1).getReg(); in runOnMachineFunction() local
76 if (MFI.isVRegStackified(Cond)) { in runOnMachineFunction()
77 assert(MRI.hasOneDef(Cond)); in runOnMachineFunction()
78 MachineInstr *Def = MRI.getVRegDef(Cond); in runOnMachineFunction()
179 Cond = Def->getOperand(1).getReg(); in runOnMachineFunction()
194 .addReg(Cond); in runOnMachineFunction()
196 Cond = Tmp; in runOnMachineFunction()
205 .addReg(Cond); in runOnMachineFunction()
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| /freebsd-12.1/contrib/llvm/lib/Transforms/Utils/ |
| H A D | LibCallsShrinkWrap.cpp | 138 Value *Cond = nullptr; in performCallDomainErrorOnly() local
183 shrinkWrapCI(CI, Cond); in performCallDomainErrorOnly()
190 Value *Cond = nullptr; in performCallRangeErrorOnly() local
208 Cond = generateTwoRangeCond(CI, Func); in performCallRangeErrorOnly()
215 Cond = generateOneRangeCond(CI, Func); in performCallRangeErrorOnly()
221 shrinkWrapCI(CI, Cond); in performCallRangeErrorOnly()
228 Value *Cond = nullptr; in performCallErrors() local
275 Cond = generateCondForPow(CI, Func); in performCallErrors()
276 if (Cond == nullptr) in performCallErrors()
284 shrinkWrapCI(CI, Cond); in performCallErrors()
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| /freebsd-12.1/contrib/llvm/lib/Target/XCore/ |
| H A D | XCoreInstrInfo.cpp | 221 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in analyzeBranch()
222 Cond.push_back(LastInst->getOperand(0)); in analyzeBranch()
242 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in analyzeBranch()
243 Cond.push_back(SecondLastInst->getOperand(0)); in analyzeBranch()
280 assert((Cond.size() == 2 || Cond.size() == 0) && in insertBranch()
285 if (Cond.empty()) { in insertBranch()
291 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()) in insertBranch()
298 assert(Cond.size() == 2 && "Unexpected number of components!"); in insertBranch()
300 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()) in insertBranch()
405 assert((Cond.size() == 2) && in reverseBranchCondition()
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| /freebsd-12.1/contrib/llvm/lib/Target/MSP430/ |
| H A D | MSP430InstrInfo.cpp | 133 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { in reverseBranchCondition()
134 assert(Cond.size() == 1 && "Invalid Xbranch condition!"); in reverseBranchCondition()
160 Cond[0].setImm(CC); in reverseBranchCondition()
179 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
214 Cond.clear(); in analyzeBranch()
238 if (Cond.empty()) { in analyzeBranch()
241 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in analyzeBranch()
247 assert(Cond.size() == 1); in analyzeBranch()
269 ArrayRef<MachineOperand> Cond, in insertBranch() argument
274 assert((Cond.size() == 1 || Cond.size() == 0) && in insertBranch()
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| /freebsd-12.1/contrib/llvm/lib/Target/ARC/ |
| H A D | ARCInstrInfo.cpp | 190 if (!Cond.empty()) in analyzeBranch()
196 Cond.push_back(I->getOperand(1)); in analyzeBranch()
197 Cond.push_back(I->getOperand(2)); in analyzeBranch()
198 Cond.push_back(I->getOperand(3)); in analyzeBranch()
213 Cond.clear(); in analyzeBranch()
339 SmallVectorImpl<MachineOperand> &Cond) const { in reverseBranchCondition()
340 assert((Cond.size() == 3) && "Invalid ARC branch condition!"); in reverseBranchCondition()
341 Cond[2].setImm(GetOppositeBranchCondition((ARCCC::CondCode)Cond[2].getImm())); in reverseBranchCondition()
367 assert((Cond.size() == 3 || Cond.size() == 0) && in insertBranch()
370 if (Cond.empty()) { in insertBranch()
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| /freebsd-12.1/contrib/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.cpp | 190 Cond.push_back(LastInst.getOperand(0)); in parseCondBranch()
191 Cond.push_back(LastInst.getOperand(1)); in parseCondBranch()
219 Cond.clear(); in analyzeBranch()
265 parseCondBranch(*I, TBB, Cond); in analyzeBranch()
272 parseCondBranch(*std::prev(I), TBB, Cond); in analyzeBranch()
323 assert((Cond.size() == 3 || Cond.size() == 0) && in insertBranch()
327 if (Cond.empty()) { in insertBranch()
335 unsigned Opc = Cond[0].getImm(); in insertBranch()
337 *BuildMI(&MBB, DL, get(Opc)).add(Cond[1]).add(Cond[2]).addMBB(TBB); in insertBranch()
395 SmallVectorImpl<MachineOperand> &Cond) const { in reverseBranchCondition()
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| /freebsd-12.1/contrib/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXInstrInfo.cpp | 99 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
117 Cond.push_back(LastInst.getOperand(0)); in analyzeBranch()
135 Cond.push_back(SecondLastInst.getOperand(0)); in analyzeBranch()
184 ArrayRef<MachineOperand> Cond, in insertBranch() argument
191 assert((Cond.size() == 1 || Cond.size() == 0) && in insertBranch()
196 if (Cond.empty()) // Unconditional branch in insertBranch()
199 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()) in insertBranch()
205 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()).addMBB(TBB); in insertBranch()
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| /freebsd-12.1/contrib/llvm/lib/Target/Mips/ |
| H A D | MipsInstrInfo.cpp | 92 Cond.push_back(Inst->getOperand(i)); in AnalyzeCondBr()
109 unsigned Opc = Cond[0].getImm(); in BuildCondBr()
113 for (unsigned i = 1; i < Cond.size(); ++i) { in BuildCondBr()
114 assert((Cond[i].isImm() || Cond[i].isReg()) && in BuildCondBr()
116 MIB.add(Cond[i]); in BuildCondBr()
136 assert((Cond.size() <= 3) && in insertBranch()
141 BuildCondBr(MBB, TBB, DL, Cond); in insertBranch()
148 if (Cond.empty()) in insertBranch()
151 BuildCondBr(MBB, TBB, DL, Cond); in insertBranch()
185 assert( (Cond.size() && Cond.size() <= 3) && in reverseBranchCondition()
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| H A D | MipsInstrInfo.h | 66 SmallVectorImpl<MachineOperand> &Cond,
73 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
78 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
82 SmallVectorImpl<MachineOperand> &Cond,
176 SmallVectorImpl<MachineOperand> &Cond) const;
179 const DebugLoc &DL, ArrayRef<MachineOperand> Cond) const;
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| /freebsd-12.1/contrib/llvm/lib/Target/AVR/ |
| H A D | AVRInstrInfo.cpp | 307 Cond.clear(); in analyzeBranch()
331 if (Cond.empty()) { in analyzeBranch()
372 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in analyzeBranch()
378 assert(Cond.size() == 1); in analyzeBranch()
402 ArrayRef<MachineOperand> Cond, in insertBranch() argument
409 assert((Cond.size() == 1 || Cond.size() == 0) && in insertBranch()
412 if (Cond.empty()) { in insertBranch()
422 AVRCC::CondCodes CC = (AVRCC::CondCodes)Cond[0].getImm(); in insertBranch()
468 SmallVectorImpl<MachineOperand> &Cond) const { in reverseBranchCondition()
469 assert(Cond.size() == 1 && "Invalid AVR branch condition!"); in reverseBranchCondition()
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| /freebsd-12.1/contrib/llvm/lib/Target/X86/ |
| H A D | X86FlagsCopyLowering.cpp | 111 DebugLoc TestLoc, X86::CondCode Cond);
115 X86::CondCode Cond, CondRegArray &CondRegs);
733 X86::CondCode Cond = X86::getCondFromSETOpc(MI.getOpcode()); in collectCondsInRegs() local
738 CondRegs[Cond] = MI.getOperand(0).getReg(); in collectCondsInRegs()
751 DebugLoc TestLoc, X86::CondCode Cond) { in promoteCondToReg() argument
764 unsigned &CondReg = CondRegs[Cond]; in getCondOrInverseInReg()
791 X86::CondCode Cond; in rewriteArithmetic() local
802 Cond = X86::COND_B; // CF == 1 in rewriteArithmetic()
809 Cond = X86::COND_O; // OF == 1 in rewriteArithmetic()
819 unsigned &CondReg = CondRegs[Cond]; in rewriteArithmetic()
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| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | SIAnnotateControlFlow.cpp | 95 handleLoopCondition(Value *Cond, PHINode *Broken, llvm::Loop *L,
225 Value *Cond, PHINode *Broken, llvm::Loop *L, BranchInst *Term) { in handleLoopCondition() argument
226 if (Instruction *Inst = dyn_cast<Instruction>(Cond)) { in handleLoopCondition()
235 Value *Args[] = { Cond, Broken }; in handleLoopCondition()
240 if (isa<Constant>(Cond)) { in handleLoopCondition()
241 Instruction *Insert = Cond == BoolTrue ? in handleLoopCondition()
244 Value *Args[] = { Cond, Broken }; in handleLoopCondition()
264 Value *Cond = Term->getCondition(); in handleLoop() local
266 Value *Arg = handleLoopCondition(Cond, Broken, L, Term); in handleLoop()
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| /freebsd-12.1/contrib/llvm/tools/clang/include/clang/StaticAnalyzer/Core/PathSensitive/ |
| H A D | ConstraintManager.h | 84 DefinedSVal Cond,
91 ProgramStatePair assumeDual(ProgramStateRef State, DefinedSVal Cond) { in assumeDual() argument
92 ProgramStateRef StTrue = assume(State, Cond, true); in assumeDual()
102 assert(assume(State, Cond, false) && "System is over constrained."); in assumeDual()
107 ProgramStateRef StFalse = assume(State, Cond, false); in assumeDual()
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| /freebsd-12.1/contrib/llvm/lib/Transforms/Scalar/ |
| H A D | LoopUnswitch.cpp | 425 auto CacheIt = Cache.find(Cond); in FindLIVLoopCondition()
433 if (Cond->getType()->isVectorTy()) in FindLIVLoopCondition()
443 Cache[Cond] = Cond; in FindLIVLoopCondition()
444 return Cond; in FindLIVLoopCondition()
483 Cache[Cond] = LHS; in FindLIVLoopCondition()
491 Cache[Cond] = RHS; in FindLIVLoopCondition()
497 Cache[Cond] = nullptr; in FindLIVLoopCondition()
571 Value *Cond = BInst->getCondition(); in isUnreachableDueToPreviousUnswitching() local
572 if (!isa<ConstantInt>(Cond)) in isUnreachableDueToPreviousUnswitching()
576 Cond == ConstantInt::getTrue(Cond->getContext()) in isUnreachableDueToPreviousUnswitching()
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| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 393 Cond.clear(); in analyzeBranch()
594 if (!Cond.empty() && Cond[0].isImm()) in insertBranch()
598 if (Cond.empty()) { in insertBranch()
1483 if (Cond.empty()) in reverseBranchCondition()
1521 if (Cond.empty() || isNewValueJump(Cond[0].getImm()) || in PredicateInstruction()
3099 if (Cond.empty() || !isPredicated(Cond[0].getImm())) in predOpcodeHasNot()
4098 if (Cond.empty()) in getInvertedPredSense()
4101 Cond[0].setImm(Opc); in getInvertedPredSense()
4218 if (Cond.empty()) in getPredReg()
4221 if (isNewValueJump(Cond[0].getImm()) || Cond[1].isMBB()) { in getPredReg()
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| H A D | HexagonInstrInfo.h | 109 SmallVectorImpl<MachineOperand> &Cond,
129 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
145 SmallVectorImpl<MachineOperand> &Cond,
225 bool reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
241 ArrayRef<MachineOperand> Cond) const override;
436 bool predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const;
461 bool getInvertedPredSense(SmallVectorImpl<MachineOperand> &Cond) const;
467 bool getPredReg(ArrayRef<MachineOperand> Cond, unsigned &PredReg,
488 bool validateBranchCond(const ArrayRef<MachineOperand> &Cond) const;
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| /freebsd-12.1/contrib/llvm/lib/Target/Sparc/ |
| H A D | SparcInstrInfo.cpp | 155 SmallVectorImpl<MachineOperand> &Cond) { in parseCondBranch() argument
184 parseCondBranch(LastInst, TBB, Cond); in analyzeBranch()
218 parseCondBranch(SecondLastInst, TBB, Cond); in analyzeBranch()
246 ArrayRef<MachineOperand> Cond, in insertBranch() argument
250 assert((Cond.size() == 1 || Cond.size() == 0) && in insertBranch()
254 if (Cond.empty()) { in insertBranch()
261 unsigned CC = Cond[0].getImm(); in insertBranch()
299 SmallVectorImpl<MachineOperand> &Cond) const { in reverseBranchCondition()
300 assert(Cond.size() == 1); in reverseBranchCondition()
301 SPCC::CondCodes CC = static_cast<SPCC::CondCodes>(Cond[0].getImm()); in reverseBranchCondition()
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| /freebsd-12.1/contrib/llvm/utils/TableGen/ |
| H A D | SubtargetFeatureInfo.cpp | 141 StringRef Cond = Comma.first; in emitComputeAssemblerAvailableFeatures() local
142 if (Cond[0] == '!') { in emitComputeAssemblerAvailableFeatures()
144 Cond = Cond.substr(1); in emitComputeAssemblerAvailableFeatures()
150 OS << "FB[" << TargetName << "::" << Cond << "])"; in emitComputeAssemblerAvailableFeatures()
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| /freebsd-12.1/contrib/llvm/lib/Support/ |
| H A D | Parallel.cpp | 82 Cond.notify_all(); in ~ThreadPoolExecutor()
90 Cond.notify_one(); in add()
97 Cond.wait(Lock, [&] { return Stop || !WorkStack.empty(); }); in work()
111 std::condition_variable Cond; member in __anon6be6bc8e0111::ThreadPoolExecutor
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| /freebsd-12.1/contrib/llvm/lib/Analysis/ |
| H A D | MustExecute.cpp | 123 if (auto *Cond = dyn_cast<ConstantInt>(BI->getCondition())) in CanProveNotTakenFirstIteration() local
124 return BI->getSuccessor(Cond->getZExtValue() ? 1 : 0) == ExitBlock; in CanProveNotTakenFirstIteration()
125 auto *Cond = dyn_cast<CmpInst>(BI->getCondition()); in CanProveNotTakenFirstIteration() local
126 if (!Cond) in CanProveNotTakenFirstIteration()
131 auto *LHS = dyn_cast<PHINode>(Cond->getOperand(0)); in CanProveNotTakenFirstIteration()
132 auto *RHS = Cond->getOperand(1); in CanProveNotTakenFirstIteration()
137 auto *SimpleValOrNull = SimplifyCmpInst(Cond->getPredicate(), in CanProveNotTakenFirstIteration()
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/ |
| H A D | MachineBasicBlock.cpp | 530 SmallVector<MachineOperand, 4> Cond; in updateTerminator() local
535 if (Cond.empty()) { in updateTerminator()
570 if (TII->reverseBranchCondition(Cond)) in updateTerminator()
611 Cond.clear(); in updateTerminator()
618 if (TII->reverseBranchCondition(Cond)) { in updateTerminator()
620 Cond.clear(); in updateTerminator()
835 SmallVector<MachineOperand, 4> Cond; in getFallThrough() local
837 if (TII->analyzeBranch(*this, TBB, FBB, Cond)) { in getFallThrough()
859 if (Cond.empty()) return nullptr; in getFallThrough()
964 SmallVector<MachineOperand, 4> Cond; in SplitCriticalEdge() local
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 2059 (Cond != ISD::SETEQ && Cond != ISD::SETNE)) in simplifySetCCWithAnd()
2240 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && in SimplifySetCC()
2283 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && in SimplifySetCC()
2622 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { in SimplifySetCC()
2642 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { in SimplifySetCC()
2662 if (Cond == ISD::SETLT || Cond == ISD::SETULT) { in SimplifySetCC()
2680 if (Cond == ISD::SETGT || Cond == ISD::SETUGT) { in SimplifySetCC()
2726 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && in SimplifySetCC()
2758 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && in SimplifySetCC()
2832 if (Cond == ISD::SETO || Cond == ISD::SETUO) in SimplifySetCC()
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| /freebsd-12.1/contrib/llvm/tools/clang/lib/Sema/ |
| H A D | ScopeInfo.cpp | 181 if (const ConditionalOperator *Cond = dyn_cast<ConditionalOperator>(E)) { in markSafeWeakUse() local
182 markSafeWeakUse(Cond->getTrueExpr()); in markSafeWeakUse()
183 markSafeWeakUse(Cond->getFalseExpr()); in markSafeWeakUse()
187 if (const BinaryConditionalOperator *Cond = in markSafeWeakUse() local
189 markSafeWeakUse(Cond->getCommon()); in markSafeWeakUse()
190 markSafeWeakUse(Cond->getFalseExpr()); in markSafeWeakUse()
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