Lines Matching refs:Cond
82 SmallVectorImpl<MachineOperand> &Cond) const { in AnalyzeCondBr()
89 Cond.push_back(MachineOperand::CreateImm(Opc)); in AnalyzeCondBr()
92 Cond.push_back(Inst->getOperand(i)); in AnalyzeCondBr()
98 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
101 BranchType BT = analyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs); in analyzeBranch()
108 ArrayRef<MachineOperand> Cond) const { in BuildCondBr()
109 unsigned Opc = Cond[0].getImm(); in BuildCondBr()
113 for (unsigned i = 1; i < Cond.size(); ++i) { in BuildCondBr()
114 assert((Cond[i].isImm() || Cond[i].isReg()) && in BuildCondBr()
116 MIB.add(Cond[i]); in BuildCondBr()
124 ArrayRef<MachineOperand> Cond, in insertBranch() argument
136 assert((Cond.size() <= 3) && in insertBranch()
141 BuildCondBr(MBB, TBB, DL, Cond); in insertBranch()
148 if (Cond.empty()) in insertBranch()
151 BuildCondBr(MBB, TBB, DL, Cond); in insertBranch()
184 SmallVectorImpl<MachineOperand> &Cond) const { in reverseBranchCondition()
185 assert( (Cond.size() && Cond.size() <= 3) && in reverseBranchCondition()
187 Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm())); in reverseBranchCondition()
193 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify, in analyzeBranch() argument
244 AnalyzeCondBr(LastInst, LastOpc, TBB, Cond); in analyzeBranch()
273 AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond); in analyzeBranch()