155                             SmallVectorImpl<MachineOperand> &Cond) {  in parseCondBranch()  argument
156   Cond.push_back(MachineOperand::CreateImm(LastInst->getOperand(1).getImm()));  in parseCondBranch()
163                                    SmallVectorImpl<MachineOperand> &Cond,  in analyzeBranch()  argument
184       parseCondBranch(LastInst, TBB, Cond);  in analyzeBranch()
218     parseCondBranch(SecondLastInst, TBB, Cond);  in analyzeBranch()
246                                       ArrayRef<MachineOperand> Cond,  in insertBranch()  argument
250   assert((Cond.size() == 1 || Cond.size() == 0) &&  in insertBranch()
254   if (Cond.empty()) {  in insertBranch()
261   unsigned CC = Cond[0].getImm();  in insertBranch()
299     SmallVectorImpl<MachineOperand> &Cond) const {  in reverseBranchCondition()
300   assert(Cond.size() == 1);  in reverseBranchCondition()
301   SPCC::CondCodes CC = static_cast<SPCC::CondCodes>(Cond[0].getImm());  in reverseBranchCondition()
302   Cond[0].setImm(GetOppositeBranchCondition(CC));  in reverseBranchCondition()