Lines Matching refs:Cond
99 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
113 Cond.push_back(MachineOperand::CreateImm(true)); in analyzeBranch()
114 Cond.push_back(MI.getOperand(1)); in analyzeBranch()
124 Cond.push_back(MachineOperand::CreateImm(false)); in analyzeBranch()
125 Cond.push_back(MI.getOperand(1)); in analyzeBranch()
170 ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const { in insertBranch() argument
173 if (Cond.empty()) { in insertBranch()
181 assert(Cond.size() == 2 && "Expected a flag and a successor block"); in insertBranch()
183 if (Cond[0].getImm()) { in insertBranch()
184 BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addMBB(TBB).add(Cond[1]); in insertBranch()
186 BuildMI(&MBB, DL, get(WebAssembly::BR_UNLESS)).addMBB(TBB).add(Cond[1]); in insertBranch()
196 SmallVectorImpl<MachineOperand> &Cond) const { in reverseBranchCondition()
197 assert(Cond.size() == 2 && "Expected a flag and a successor block"); in reverseBranchCondition()
198 Cond.front() = MachineOperand::CreateImm(!Cond.front().getImm()); in reverseBranchCondition()