| 6b0856ee | 10-Apr-2024 |
Samuel Holland <[email protected]> |
cache: sifive_ccache: Silence unused variable warning
With W=1 and CONFIG_RISCV_NONSTANDARD_CACHE_OPS=n, GCC warns:
drivers/cache/sifive_ccache.c: In function 'sifive_ccache_init':
drivers/cache/si
cache: sifive_ccache: Silence unused variable warning
With W=1 and CONFIG_RISCV_NONSTANDARD_CACHE_OPS=n, GCC warns:
drivers/cache/sifive_ccache.c: In function 'sifive_ccache_init':
drivers/cache/sifive_ccache.c:293:23: warning: variable 'quirks' set but not used [-Wunused-but-set-variable]
293 | unsigned long quirks;
| ^~~~~~
This is expected, since QUIRK_NONSTANDARD_CACHE_OPS is the only quirk
still handled in this function.
Fixes: c90847bcbfb6 ("cache: sifive_ccache: Partially convert to a platform driver")
Reported-by: kernel test robot <[email protected]>
Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
Signed-off-by: Samuel Holland <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
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|
| 0d5701dc | 31-Oct-2023 |
Emil Renner Berthing <[email protected]> |
soc: sifive: ccache: Add StarFive JH7100 support
This adds support for the StarFive JH7100 SoC which also features this
SiFive cache controller.
The JH7100 has non-coherent DMAs but predate the sta
soc: sifive: ccache: Add StarFive JH7100 support
This adds support for the StarFive JH7100 SoC which also features this
SiFive cache controller.
The JH7100 has non-coherent DMAs but predate the standard RISC-V Zicbom
exension, so instead we need to use this cache controller for
non-standard cache management operations.
Unfortunately the interrupt for uncorrected data is broken on the JH7100
and fires continuously, so add a quirk to not register a handler for it.
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
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|