1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/string.h> 27 #include <linux/acpi.h> 28 #include <linux/i2c.h> 29 30 #include <drm/drm_atomic.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/amdgpu_drm.h> 33 #include <drm/drm_edid.h> 34 35 #include "dm_services.h" 36 #include "amdgpu.h" 37 #include "dc.h" 38 #include "amdgpu_dm.h" 39 #include "amdgpu_dm_irq.h" 40 #include "amdgpu_dm_mst_types.h" 41 #include "dpcd_defs.h" 42 #include "dc/inc/core_types.h" 43 44 #include "dm_helpers.h" 45 #include "ddc_service_types.h" 46 47 static u32 edid_extract_panel_id(struct edid *edid) 48 { 49 return (u32)edid->mfg_id[0] << 24 | 50 (u32)edid->mfg_id[1] << 16 | 51 (u32)EDID_PRODUCT_ID(edid); 52 } 53 54 static void apply_edid_quirks(struct edid *edid, struct dc_edid_caps *edid_caps) 55 { 56 uint32_t panel_id = edid_extract_panel_id(edid); 57 58 switch (panel_id) { 59 /* Workaround for some monitors which does not work well with FAMS */ 60 case drm_edid_encode_panel_id('S', 'A', 'M', 0x0E5E): 61 case drm_edid_encode_panel_id('S', 'A', 'M', 0x7053): 62 case drm_edid_encode_panel_id('S', 'A', 'M', 0x71AC): 63 DRM_DEBUG_DRIVER("Disabling FAMS on monitor with panel id %X\n", panel_id); 64 edid_caps->panel_patch.disable_fams = true; 65 break; 66 default: 67 return; 68 } 69 } 70 71 /* dm_helpers_parse_edid_caps 72 * 73 * Parse edid caps 74 * 75 * @edid: [in] pointer to edid 76 * edid_caps: [in] pointer to edid caps 77 * @return 78 * void 79 * */ 80 enum dc_edid_status dm_helpers_parse_edid_caps( 81 struct dc_link *link, 82 const struct dc_edid *edid, 83 struct dc_edid_caps *edid_caps) 84 { 85 struct amdgpu_dm_connector *aconnector = link->priv; 86 struct drm_connector *connector = &aconnector->base; 87 struct edid *edid_buf = edid ? (struct edid *) edid->raw_edid : NULL; 88 struct cea_sad *sads; 89 int sad_count = -1; 90 int sadb_count = -1; 91 int i = 0; 92 uint8_t *sadb = NULL; 93 94 enum dc_edid_status result = EDID_OK; 95 96 if (!edid_caps || !edid) 97 return EDID_BAD_INPUT; 98 99 if (!drm_edid_is_valid(edid_buf)) 100 result = EDID_BAD_CHECKSUM; 101 102 edid_caps->manufacturer_id = (uint16_t) edid_buf->mfg_id[0] | 103 ((uint16_t) edid_buf->mfg_id[1])<<8; 104 edid_caps->product_id = (uint16_t) edid_buf->prod_code[0] | 105 ((uint16_t) edid_buf->prod_code[1])<<8; 106 edid_caps->serial_number = edid_buf->serial; 107 edid_caps->manufacture_week = edid_buf->mfg_week; 108 edid_caps->manufacture_year = edid_buf->mfg_year; 109 110 drm_edid_get_monitor_name(edid_buf, 111 edid_caps->display_name, 112 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); 113 114 edid_caps->edid_hdmi = connector->display_info.is_hdmi; 115 116 sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads); 117 if (sad_count <= 0) 118 return result; 119 120 edid_caps->audio_mode_count = sad_count < DC_MAX_AUDIO_DESC_COUNT ? sad_count : DC_MAX_AUDIO_DESC_COUNT; 121 for (i = 0; i < edid_caps->audio_mode_count; ++i) { 122 struct cea_sad *sad = &sads[i]; 123 124 edid_caps->audio_modes[i].format_code = sad->format; 125 edid_caps->audio_modes[i].channel_count = sad->channels + 1; 126 edid_caps->audio_modes[i].sample_rate = sad->freq; 127 edid_caps->audio_modes[i].sample_size = sad->byte2; 128 } 129 130 sadb_count = drm_edid_to_speaker_allocation((struct edid *) edid->raw_edid, &sadb); 131 132 if (sadb_count < 0) { 133 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sadb_count); 134 sadb_count = 0; 135 } 136 137 if (sadb_count) 138 edid_caps->speaker_flags = sadb[0]; 139 else 140 edid_caps->speaker_flags = DEFAULT_SPEAKER_LOCATION; 141 142 apply_edid_quirks(edid_buf, edid_caps); 143 144 kfree(sads); 145 kfree(sadb); 146 147 return result; 148 } 149 150 static void 151 fill_dc_mst_payload_table_from_drm(struct dc_link *link, 152 bool enable, 153 struct drm_dp_mst_atomic_payload *target_payload, 154 struct dc_dp_mst_stream_allocation_table *table) 155 { 156 struct dc_dp_mst_stream_allocation_table new_table = { 0 }; 157 struct dc_dp_mst_stream_allocation *sa; 158 struct link_mst_stream_allocation_table copy_of_link_table = 159 link->mst_stream_alloc_table; 160 161 int i; 162 int current_hw_table_stream_cnt = copy_of_link_table.stream_count; 163 struct link_mst_stream_allocation *dc_alloc; 164 165 /* TODO: refactor to set link->mst_stream_alloc_table directly if possible.*/ 166 if (enable) { 167 dc_alloc = 168 ©_of_link_table.stream_allocations[current_hw_table_stream_cnt]; 169 dc_alloc->vcp_id = target_payload->vcpi; 170 dc_alloc->slot_count = target_payload->time_slots; 171 } else { 172 for (i = 0; i < copy_of_link_table.stream_count; i++) { 173 dc_alloc = 174 ©_of_link_table.stream_allocations[i]; 175 176 if (dc_alloc->vcp_id == target_payload->vcpi) { 177 dc_alloc->vcp_id = 0; 178 dc_alloc->slot_count = 0; 179 break; 180 } 181 } 182 ASSERT(i != copy_of_link_table.stream_count); 183 } 184 185 /* Fill payload info*/ 186 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 187 dc_alloc = 188 ©_of_link_table.stream_allocations[i]; 189 if (dc_alloc->vcp_id > 0 && dc_alloc->slot_count > 0) { 190 sa = &new_table.stream_allocations[new_table.stream_count]; 191 sa->slot_count = dc_alloc->slot_count; 192 sa->vcp_id = dc_alloc->vcp_id; 193 new_table.stream_count++; 194 } 195 } 196 197 /* Overwrite the old table */ 198 *table = new_table; 199 } 200 201 void dm_helpers_dp_update_branch_info( 202 struct dc_context *ctx, 203 const struct dc_link *link) 204 {} 205 206 static void dm_helpers_construct_old_payload( 207 struct dc_link *link, 208 int pbn_per_slot, 209 struct drm_dp_mst_atomic_payload *new_payload, 210 struct drm_dp_mst_atomic_payload *old_payload) 211 { 212 struct link_mst_stream_allocation_table current_link_table = 213 link->mst_stream_alloc_table; 214 struct link_mst_stream_allocation *dc_alloc; 215 int i; 216 217 *old_payload = *new_payload; 218 219 /* Set correct time_slots/PBN of old payload. 220 * other fields (delete & dsc_enabled) in 221 * struct drm_dp_mst_atomic_payload are don't care fields 222 * while calling drm_dp_remove_payload() 223 */ 224 for (i = 0; i < current_link_table.stream_count; i++) { 225 dc_alloc = 226 ¤t_link_table.stream_allocations[i]; 227 228 if (dc_alloc->vcp_id == new_payload->vcpi) { 229 old_payload->time_slots = dc_alloc->slot_count; 230 old_payload->pbn = dc_alloc->slot_count * pbn_per_slot; 231 break; 232 } 233 } 234 235 /* make sure there is an old payload*/ 236 ASSERT(i != current_link_table.stream_count); 237 238 } 239 240 /* 241 * Writes payload allocation table in immediate downstream device. 242 */ 243 bool dm_helpers_dp_mst_write_payload_allocation_table( 244 struct dc_context *ctx, 245 const struct dc_stream_state *stream, 246 struct dc_dp_mst_stream_allocation_table *proposed_table, 247 bool enable) 248 { 249 struct amdgpu_dm_connector *aconnector; 250 struct drm_dp_mst_topology_state *mst_state; 251 struct drm_dp_mst_atomic_payload *target_payload, *new_payload, old_payload; 252 struct drm_dp_mst_topology_mgr *mst_mgr; 253 254 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 255 /* Accessing the connector state is required for vcpi_slots allocation 256 * and directly relies on behaviour in commit check 257 * that blocks before commit guaranteeing that the state 258 * is not gonna be swapped while still in use in commit tail */ 259 260 if (!aconnector || !aconnector->mst_root) 261 return false; 262 263 mst_mgr = &aconnector->mst_root->mst_mgr; 264 mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state); 265 266 /* It's OK for this to fail */ 267 new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port); 268 269 if (enable) { 270 target_payload = new_payload; 271 272 drm_dp_add_payload_part1(mst_mgr, mst_state, new_payload); 273 } else { 274 /* construct old payload by VCPI*/ 275 dm_helpers_construct_old_payload(stream->link, mst_state->pbn_div, 276 new_payload, &old_payload); 277 target_payload = &old_payload; 278 279 drm_dp_remove_payload(mst_mgr, mst_state, &old_payload, new_payload); 280 } 281 282 /* mst_mgr->->payloads are VC payload notify MST branch using DPCD or 283 * AUX message. The sequence is slot 1-63 allocated sequence for each 284 * stream. AMD ASIC stream slot allocation should follow the same 285 * sequence. copy DRM MST allocation to dc */ 286 fill_dc_mst_payload_table_from_drm(stream->link, enable, target_payload, proposed_table); 287 288 return true; 289 } 290 291 /* 292 * poll pending down reply 293 */ 294 void dm_helpers_dp_mst_poll_pending_down_reply( 295 struct dc_context *ctx, 296 const struct dc_link *link) 297 {} 298 299 /* 300 * Clear payload allocation table before enable MST DP link. 301 */ 302 void dm_helpers_dp_mst_clear_payload_allocation_table( 303 struct dc_context *ctx, 304 const struct dc_link *link) 305 {} 306 307 /* 308 * Polls for ACT (allocation change trigger) handled and sends 309 * ALLOCATE_PAYLOAD message. 310 */ 311 enum act_return_status dm_helpers_dp_mst_poll_for_allocation_change_trigger( 312 struct dc_context *ctx, 313 const struct dc_stream_state *stream) 314 { 315 struct amdgpu_dm_connector *aconnector; 316 struct drm_dp_mst_topology_mgr *mst_mgr; 317 int ret; 318 319 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 320 321 if (!aconnector || !aconnector->mst_root) 322 return ACT_FAILED; 323 324 mst_mgr = &aconnector->mst_root->mst_mgr; 325 326 if (!mst_mgr->mst_state) 327 return ACT_FAILED; 328 329 ret = drm_dp_check_act_status(mst_mgr); 330 331 if (ret) 332 return ACT_FAILED; 333 334 return ACT_SUCCESS; 335 } 336 337 bool dm_helpers_dp_mst_send_payload_allocation( 338 struct dc_context *ctx, 339 const struct dc_stream_state *stream, 340 bool enable) 341 { 342 struct amdgpu_dm_connector *aconnector; 343 struct drm_dp_mst_topology_state *mst_state; 344 struct drm_dp_mst_topology_mgr *mst_mgr; 345 struct drm_dp_mst_atomic_payload *payload; 346 enum mst_progress_status set_flag = MST_ALLOCATE_NEW_PAYLOAD; 347 enum mst_progress_status clr_flag = MST_CLEAR_ALLOCATED_PAYLOAD; 348 int ret = 0; 349 350 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 351 352 if (!aconnector || !aconnector->mst_root) 353 return false; 354 355 mst_mgr = &aconnector->mst_root->mst_mgr; 356 mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state); 357 358 payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port); 359 360 if (!enable) { 361 set_flag = MST_CLEAR_ALLOCATED_PAYLOAD; 362 clr_flag = MST_ALLOCATE_NEW_PAYLOAD; 363 } 364 365 if (enable) 366 ret = drm_dp_add_payload_part2(mst_mgr, mst_state->base.state, payload); 367 368 if (ret) { 369 amdgpu_dm_set_mst_status(&aconnector->mst_status, 370 set_flag, false); 371 } else { 372 amdgpu_dm_set_mst_status(&aconnector->mst_status, 373 set_flag, true); 374 amdgpu_dm_set_mst_status(&aconnector->mst_status, 375 clr_flag, false); 376 } 377 378 return true; 379 } 380 381 void dm_dtn_log_begin(struct dc_context *ctx, 382 struct dc_log_buffer_ctx *log_ctx) 383 { 384 static const char msg[] = "[dtn begin]\n"; 385 386 if (!log_ctx) { 387 pr_info("%s", msg); 388 return; 389 } 390 391 dm_dtn_log_append_v(ctx, log_ctx, "%s", msg); 392 } 393 394 __printf(3, 4) 395 void dm_dtn_log_append_v(struct dc_context *ctx, 396 struct dc_log_buffer_ctx *log_ctx, 397 const char *msg, ...) 398 { 399 va_list args; 400 size_t total; 401 int n; 402 403 if (!log_ctx) { 404 /* No context, redirect to dmesg. */ 405 struct va_format vaf; 406 407 vaf.fmt = msg; 408 vaf.va = &args; 409 410 va_start(args, msg); 411 pr_info("%pV", &vaf); 412 va_end(args); 413 414 return; 415 } 416 417 /* Measure the output. */ 418 va_start(args, msg); 419 n = vsnprintf(NULL, 0, msg, args); 420 va_end(args); 421 422 if (n <= 0) 423 return; 424 425 /* Reallocate the string buffer as needed. */ 426 total = log_ctx->pos + n + 1; 427 428 if (total > log_ctx->size) { 429 char *buf = (char *)kvcalloc(total, sizeof(char), GFP_KERNEL); 430 431 if (buf) { 432 memcpy(buf, log_ctx->buf, log_ctx->pos); 433 kfree(log_ctx->buf); 434 435 log_ctx->buf = buf; 436 log_ctx->size = total; 437 } 438 } 439 440 if (!log_ctx->buf) 441 return; 442 443 /* Write the formatted string to the log buffer. */ 444 va_start(args, msg); 445 n = vscnprintf( 446 log_ctx->buf + log_ctx->pos, 447 log_ctx->size - log_ctx->pos, 448 msg, 449 args); 450 va_end(args); 451 452 if (n > 0) 453 log_ctx->pos += n; 454 } 455 456 void dm_dtn_log_end(struct dc_context *ctx, 457 struct dc_log_buffer_ctx *log_ctx) 458 { 459 static const char msg[] = "[dtn end]\n"; 460 461 if (!log_ctx) { 462 pr_info("%s", msg); 463 return; 464 } 465 466 dm_dtn_log_append_v(ctx, log_ctx, "%s", msg); 467 } 468 469 bool dm_helpers_dp_mst_start_top_mgr( 470 struct dc_context *ctx, 471 const struct dc_link *link, 472 bool boot) 473 { 474 struct amdgpu_dm_connector *aconnector = link->priv; 475 int ret; 476 477 if (!aconnector) { 478 DRM_ERROR("Failed to find connector for link!"); 479 return false; 480 } 481 482 if (boot) { 483 DRM_INFO("DM_MST: Differing MST start on aconnector: %p [id: %d]\n", 484 aconnector, aconnector->base.base.id); 485 return true; 486 } 487 488 DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n", 489 aconnector, aconnector->base.base.id); 490 491 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 492 if (ret < 0) { 493 DRM_ERROR("DM_MST: Failed to set the device into MST mode!"); 494 return false; 495 } 496 497 DRM_INFO("DM_MST: DP%x, %d-lane link detected\n", aconnector->mst_mgr.dpcd[0], 498 aconnector->mst_mgr.dpcd[2] & DP_MAX_LANE_COUNT_MASK); 499 500 return true; 501 } 502 503 bool dm_helpers_dp_mst_stop_top_mgr( 504 struct dc_context *ctx, 505 struct dc_link *link) 506 { 507 struct amdgpu_dm_connector *aconnector = link->priv; 508 509 if (!aconnector) { 510 DRM_ERROR("Failed to find connector for link!"); 511 return false; 512 } 513 514 DRM_INFO("DM_MST: stopping TM on aconnector: %p [id: %d]\n", 515 aconnector, aconnector->base.base.id); 516 517 if (aconnector->mst_mgr.mst_state == true) { 518 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false); 519 link->cur_link_settings.lane_count = 0; 520 } 521 522 return false; 523 } 524 525 bool dm_helpers_dp_read_dpcd( 526 struct dc_context *ctx, 527 const struct dc_link *link, 528 uint32_t address, 529 uint8_t *data, 530 uint32_t size) 531 { 532 533 struct amdgpu_dm_connector *aconnector = link->priv; 534 535 if (!aconnector) { 536 DC_LOG_DC("Failed to find connector for link!\n"); 537 return false; 538 } 539 540 return drm_dp_dpcd_read(&aconnector->dm_dp_aux.aux, address, data, 541 size) == size; 542 } 543 544 bool dm_helpers_dp_write_dpcd( 545 struct dc_context *ctx, 546 const struct dc_link *link, 547 uint32_t address, 548 const uint8_t *data, 549 uint32_t size) 550 { 551 struct amdgpu_dm_connector *aconnector = link->priv; 552 553 if (!aconnector) { 554 DRM_ERROR("Failed to find connector for link!"); 555 return false; 556 } 557 558 return drm_dp_dpcd_write(&aconnector->dm_dp_aux.aux, 559 address, (uint8_t *)data, size) > 0; 560 } 561 562 bool dm_helpers_submit_i2c( 563 struct dc_context *ctx, 564 const struct dc_link *link, 565 struct i2c_command *cmd) 566 { 567 struct amdgpu_dm_connector *aconnector = link->priv; 568 struct i2c_msg *msgs; 569 int i = 0; 570 int num = cmd->number_of_payloads; 571 bool result; 572 573 if (!aconnector) { 574 DRM_ERROR("Failed to find connector for link!"); 575 return false; 576 } 577 578 msgs = kcalloc(num, sizeof(struct i2c_msg), GFP_KERNEL); 579 580 if (!msgs) 581 return false; 582 583 for (i = 0; i < num; i++) { 584 msgs[i].flags = cmd->payloads[i].write ? 0 : I2C_M_RD; 585 msgs[i].addr = cmd->payloads[i].address; 586 msgs[i].len = cmd->payloads[i].length; 587 msgs[i].buf = cmd->payloads[i].data; 588 } 589 590 result = i2c_transfer(&aconnector->i2c->base, msgs, num) == num; 591 592 kfree(msgs); 593 594 return result; 595 } 596 597 static bool execute_synaptics_rc_command(struct drm_dp_aux *aux, 598 bool is_write_cmd, 599 unsigned char cmd, 600 unsigned int length, 601 unsigned int offset, 602 unsigned char *data) 603 { 604 bool success = false; 605 unsigned char rc_data[16] = {0}; 606 unsigned char rc_offset[4] = {0}; 607 unsigned char rc_length[2] = {0}; 608 unsigned char rc_cmd = 0; 609 unsigned char rc_result = 0xFF; 610 unsigned char i = 0; 611 int ret; 612 613 if (is_write_cmd) { 614 // write rc data 615 memmove(rc_data, data, length); 616 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_DATA, rc_data, sizeof(rc_data)); 617 } 618 619 // write rc offset 620 rc_offset[0] = (unsigned char) offset & 0xFF; 621 rc_offset[1] = (unsigned char) (offset >> 8) & 0xFF; 622 rc_offset[2] = (unsigned char) (offset >> 16) & 0xFF; 623 rc_offset[3] = (unsigned char) (offset >> 24) & 0xFF; 624 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_OFFSET, rc_offset, sizeof(rc_offset)); 625 626 // write rc length 627 rc_length[0] = (unsigned char) length & 0xFF; 628 rc_length[1] = (unsigned char) (length >> 8) & 0xFF; 629 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_LENGTH, rc_length, sizeof(rc_length)); 630 631 // write rc cmd 632 rc_cmd = cmd | 0x80; 633 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd)); 634 635 if (ret < 0) { 636 DRM_ERROR(" execute_synaptics_rc_command - write cmd ..., err = %d\n", ret); 637 return false; 638 } 639 640 // poll until active is 0 641 for (i = 0; i < 10; i++) { 642 drm_dp_dpcd_read(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd)); 643 if (rc_cmd == cmd) 644 // active is 0 645 break; 646 msleep(10); 647 } 648 649 // read rc result 650 drm_dp_dpcd_read(aux, SYNAPTICS_RC_RESULT, &rc_result, sizeof(rc_result)); 651 success = (rc_result == 0); 652 653 if (success && !is_write_cmd) { 654 // read rc data 655 drm_dp_dpcd_read(aux, SYNAPTICS_RC_DATA, data, length); 656 } 657 658 DC_LOG_DC(" execute_synaptics_rc_command - success = %d\n", success); 659 660 return success; 661 } 662 663 static void apply_synaptics_fifo_reset_wa(struct drm_dp_aux *aux) 664 { 665 unsigned char data[16] = {0}; 666 667 DC_LOG_DC("Start apply_synaptics_fifo_reset_wa\n"); 668 669 // Step 2 670 data[0] = 'P'; 671 data[1] = 'R'; 672 data[2] = 'I'; 673 data[3] = 'U'; 674 data[4] = 'S'; 675 676 if (!execute_synaptics_rc_command(aux, true, 0x01, 5, 0, data)) 677 return; 678 679 // Step 3 and 4 680 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data)) 681 return; 682 683 data[0] &= (~(1 << 1)); // set bit 1 to 0 684 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data)) 685 return; 686 687 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data)) 688 return; 689 690 data[0] &= (~(1 << 1)); // set bit 1 to 0 691 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220D98, data)) 692 return; 693 694 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data)) 695 return; 696 697 data[0] &= (~(1 << 1)); // set bit 1 to 0 698 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data)) 699 return; 700 701 // Step 3 and 5 702 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data)) 703 return; 704 705 data[0] |= (1 << 1); // set bit 1 to 1 706 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data)) 707 return; 708 709 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data)) 710 return; 711 712 data[0] |= (1 << 1); // set bit 1 to 1 713 714 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data)) 715 return; 716 717 data[0] |= (1 << 1); // set bit 1 to 1 718 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data)) 719 return; 720 721 // Step 6 722 if (!execute_synaptics_rc_command(aux, true, 0x02, 0, 0, NULL)) 723 return; 724 725 DC_LOG_DC("Done apply_synaptics_fifo_reset_wa\n"); 726 } 727 728 /* MST Dock */ 729 static const uint8_t SYNAPTICS_DEVICE_ID[] = "SYNA"; 730 731 static uint8_t write_dsc_enable_synaptics_non_virtual_dpcd_mst( 732 struct drm_dp_aux *aux, 733 const struct dc_stream_state *stream, 734 bool enable) 735 { 736 uint8_t ret = 0; 737 738 DC_LOG_DC("Configure DSC to non-virtual dpcd synaptics\n"); 739 740 if (enable) { 741 /* When DSC is enabled on previous boot and reboot with the hub, 742 * there is a chance that Synaptics hub gets stuck during reboot sequence. 743 * Applying a workaround to reset Synaptics SDP fifo before enabling the first stream 744 */ 745 if (!stream->link->link_status.link_active && 746 memcmp(stream->link->dpcd_caps.branch_dev_name, 747 (int8_t *)SYNAPTICS_DEVICE_ID, 4) == 0) 748 apply_synaptics_fifo_reset_wa(aux); 749 750 ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1); 751 DRM_INFO("Send DSC enable to synaptics\n"); 752 753 } else { 754 /* Synaptics hub not support virtual dpcd, 755 * external monitor occur garbage while disable DSC, 756 * Disable DSC only when entire link status turn to false, 757 */ 758 if (!stream->link->link_status.link_active) { 759 ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1); 760 DRM_INFO("Send DSC disable to synaptics\n"); 761 } 762 } 763 764 return ret; 765 } 766 767 bool dm_helpers_dp_write_dsc_enable( 768 struct dc_context *ctx, 769 const struct dc_stream_state *stream, 770 bool enable) 771 { 772 static const uint8_t DSC_DISABLE; 773 static const uint8_t DSC_DECODING = 0x01; 774 static const uint8_t DSC_PASSTHROUGH = 0x02; 775 776 struct amdgpu_dm_connector *aconnector; 777 struct drm_dp_mst_port *port; 778 uint8_t enable_dsc = enable ? DSC_DECODING : DSC_DISABLE; 779 uint8_t enable_passthrough = enable ? DSC_PASSTHROUGH : DSC_DISABLE; 780 uint8_t ret = 0; 781 782 if (!stream) 783 return false; 784 785 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 786 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 787 788 if (!aconnector->dsc_aux) 789 return false; 790 791 // apply w/a to synaptics 792 if (needs_dsc_aux_workaround(aconnector->dc_link) && 793 (aconnector->mst_downstream_port_present.byte & 0x7) != 0x3) 794 return write_dsc_enable_synaptics_non_virtual_dpcd_mst( 795 aconnector->dsc_aux, stream, enable_dsc); 796 797 port = aconnector->mst_output_port; 798 799 if (enable) { 800 if (port->passthrough_aux) { 801 ret = drm_dp_dpcd_write(port->passthrough_aux, 802 DP_DSC_ENABLE, 803 &enable_passthrough, 1); 804 DC_LOG_DC("Sent DSC pass-through enable to virtual dpcd port, ret = %u\n", 805 ret); 806 } 807 808 ret = drm_dp_dpcd_write(aconnector->dsc_aux, 809 DP_DSC_ENABLE, &enable_dsc, 1); 810 DC_LOG_DC("Sent DSC decoding enable to %s port, ret = %u\n", 811 (port->passthrough_aux) ? "remote RX" : 812 "virtual dpcd", 813 ret); 814 } else { 815 ret = drm_dp_dpcd_write(aconnector->dsc_aux, 816 DP_DSC_ENABLE, &enable_dsc, 1); 817 DC_LOG_DC("Sent DSC decoding disable to %s port, ret = %u\n", 818 (port->passthrough_aux) ? "remote RX" : 819 "virtual dpcd", 820 ret); 821 822 if (port->passthrough_aux) { 823 ret = drm_dp_dpcd_write(port->passthrough_aux, 824 DP_DSC_ENABLE, 825 &enable_passthrough, 1); 826 DC_LOG_DC("Sent DSC pass-through disable to virtual dpcd port, ret = %u\n", 827 ret); 828 } 829 } 830 } 831 832 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT || stream->signal == SIGNAL_TYPE_EDP) { 833 if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) { 834 ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1); 835 DC_LOG_DC("Send DSC %s to SST RX\n", enable_dsc ? "enable" : "disable"); 836 } else if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) { 837 ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1); 838 DC_LOG_DC("Send DSC %s to DP-HDMI PCON\n", enable_dsc ? "enable" : "disable"); 839 } 840 } 841 842 return ret; 843 } 844 845 bool dm_helpers_is_dp_sink_present(struct dc_link *link) 846 { 847 bool dp_sink_present; 848 struct amdgpu_dm_connector *aconnector = link->priv; 849 850 if (!aconnector) { 851 BUG_ON("Failed to find connector for link!"); 852 return true; 853 } 854 855 mutex_lock(&aconnector->dm_dp_aux.aux.hw_mutex); 856 dp_sink_present = dc_link_is_dp_sink_present(link); 857 mutex_unlock(&aconnector->dm_dp_aux.aux.hw_mutex); 858 return dp_sink_present; 859 } 860 861 enum dc_edid_status dm_helpers_read_local_edid( 862 struct dc_context *ctx, 863 struct dc_link *link, 864 struct dc_sink *sink) 865 { 866 struct amdgpu_dm_connector *aconnector = link->priv; 867 struct drm_connector *connector = &aconnector->base; 868 struct i2c_adapter *ddc; 869 int retry = 3; 870 enum dc_edid_status edid_status; 871 struct edid *edid; 872 873 if (link->aux_mode) 874 ddc = &aconnector->dm_dp_aux.aux.ddc; 875 else 876 ddc = &aconnector->i2c->base; 877 878 /* some dongles read edid incorrectly the first time, 879 * do check sum and retry to make sure read correct edid. 880 */ 881 do { 882 883 edid = drm_get_edid(&aconnector->base, ddc); 884 885 /* DP Compliance Test 4.2.2.6 */ 886 if (link->aux_mode && connector->edid_corrupt) 887 drm_dp_send_real_edid_checksum(&aconnector->dm_dp_aux.aux, connector->real_edid_checksum); 888 889 if (!edid && connector->edid_corrupt) { 890 connector->edid_corrupt = false; 891 return EDID_BAD_CHECKSUM; 892 } 893 894 if (!edid) 895 return EDID_NO_RESPONSE; 896 897 sink->dc_edid.length = EDID_LENGTH * (edid->extensions + 1); 898 memmove(sink->dc_edid.raw_edid, (uint8_t *)edid, sink->dc_edid.length); 899 900 /* We don't need the original edid anymore */ 901 kfree(edid); 902 903 edid_status = dm_helpers_parse_edid_caps( 904 link, 905 &sink->dc_edid, 906 &sink->edid_caps); 907 908 } while (edid_status == EDID_BAD_CHECKSUM && --retry > 0); 909 910 if (edid_status != EDID_OK) 911 DRM_ERROR("EDID err: %d, on connector: %s", 912 edid_status, 913 aconnector->base.name); 914 if (link->aux_mode) { 915 union test_request test_request = {0}; 916 union test_response test_response = {0}; 917 918 dm_helpers_dp_read_dpcd(ctx, 919 link, 920 DP_TEST_REQUEST, 921 &test_request.raw, 922 sizeof(union test_request)); 923 924 if (!test_request.bits.EDID_READ) 925 return edid_status; 926 927 test_response.bits.EDID_CHECKSUM_WRITE = 1; 928 929 dm_helpers_dp_write_dpcd(ctx, 930 link, 931 DP_TEST_EDID_CHECKSUM, 932 &sink->dc_edid.raw_edid[sink->dc_edid.length-1], 933 1); 934 935 dm_helpers_dp_write_dpcd(ctx, 936 link, 937 DP_TEST_RESPONSE, 938 &test_response.raw, 939 sizeof(test_response)); 940 941 } 942 943 return edid_status; 944 } 945 int dm_helper_dmub_aux_transfer_sync( 946 struct dc_context *ctx, 947 const struct dc_link *link, 948 struct aux_payload *payload, 949 enum aux_return_code_type *operation_result) 950 { 951 return amdgpu_dm_process_dmub_aux_transfer_sync(ctx, link->link_index, payload, 952 operation_result); 953 } 954 955 int dm_helpers_dmub_set_config_sync(struct dc_context *ctx, 956 const struct dc_link *link, 957 struct set_config_cmd_payload *payload, 958 enum set_config_status *operation_result) 959 { 960 return amdgpu_dm_process_dmub_set_config_sync(ctx, link->link_index, payload, 961 operation_result); 962 } 963 964 void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks) 965 { 966 /* TODO: something */ 967 } 968 969 void dm_helpers_smu_timeout(struct dc_context *ctx, unsigned int msg_id, unsigned int param, unsigned int timeout_us) 970 { 971 // TODO: 972 //amdgpu_device_gpu_recover(dc_context->driver-context, NULL); 973 } 974 975 void dm_helpers_init_panel_settings( 976 struct dc_context *ctx, 977 struct dc_panel_config *panel_config, 978 struct dc_sink *sink) 979 { 980 // Extra Panel Power Sequence 981 panel_config->pps.extra_t3_ms = sink->edid_caps.panel_patch.extra_t3_ms; 982 panel_config->pps.extra_t7_ms = sink->edid_caps.panel_patch.extra_t7_ms; 983 panel_config->pps.extra_delay_backlight_off = sink->edid_caps.panel_patch.extra_delay_backlight_off; 984 panel_config->pps.extra_post_t7_ms = 0; 985 panel_config->pps.extra_pre_t11_ms = 0; 986 panel_config->pps.extra_t12_ms = sink->edid_caps.panel_patch.extra_t12_ms; 987 panel_config->pps.extra_post_OUI_ms = 0; 988 // Feature DSC 989 panel_config->dsc.disable_dsc_edp = false; 990 panel_config->dsc.force_dsc_edp_policy = 0; 991 } 992 993 void dm_helpers_override_panel_settings( 994 struct dc_context *ctx, 995 struct dc_panel_config *panel_config) 996 { 997 // Feature DSC 998 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) { 999 panel_config->dsc.disable_dsc_edp = true; 1000 } 1001 } 1002 1003 void *dm_helpers_allocate_gpu_mem( 1004 struct dc_context *ctx, 1005 enum dc_gpu_mem_alloc_type type, 1006 size_t size, 1007 long long *addr) 1008 { 1009 struct amdgpu_device *adev = ctx->driver_context; 1010 struct dal_allocation *da; 1011 u32 domain = (type == DC_MEM_ALLOC_TYPE_GART) ? 1012 AMDGPU_GEM_DOMAIN_GTT : AMDGPU_GEM_DOMAIN_VRAM; 1013 int ret; 1014 1015 da = kzalloc(sizeof(struct dal_allocation), GFP_KERNEL); 1016 if (!da) 1017 return NULL; 1018 1019 ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE, 1020 domain, &da->bo, 1021 &da->gpu_addr, &da->cpu_ptr); 1022 1023 *addr = da->gpu_addr; 1024 1025 if (ret) { 1026 kfree(da); 1027 return NULL; 1028 } 1029 1030 /* add da to list in dm */ 1031 list_add(&da->list, &adev->dm.da_list); 1032 1033 return da->cpu_ptr; 1034 } 1035 1036 void dm_helpers_free_gpu_mem( 1037 struct dc_context *ctx, 1038 enum dc_gpu_mem_alloc_type type, 1039 void *pvMem) 1040 { 1041 struct amdgpu_device *adev = ctx->driver_context; 1042 struct dal_allocation *da; 1043 1044 /* walk the da list in DM */ 1045 list_for_each_entry(da, &adev->dm.da_list, list) { 1046 if (pvMem == da->cpu_ptr) { 1047 amdgpu_bo_free_kernel(&da->bo, &da->gpu_addr, &da->cpu_ptr); 1048 list_del(&da->list); 1049 kfree(da); 1050 break; 1051 } 1052 } 1053 } 1054 1055 bool dm_helpers_dmub_outbox_interrupt_control(struct dc_context *ctx, bool enable) 1056 { 1057 enum dc_irq_source irq_source; 1058 bool ret; 1059 1060 irq_source = DC_IRQ_SOURCE_DMCUB_OUTBOX; 1061 1062 ret = dc_interrupt_set(ctx->dc, irq_source, enable); 1063 1064 DRM_DEBUG_DRIVER("Dmub trace irq %sabling: r=%d\n", 1065 enable ? "en" : "dis", ret); 1066 return ret; 1067 } 1068 1069 void dm_helpers_mst_enable_stream_features(const struct dc_stream_state *stream) 1070 { 1071 /* TODO: virtual DPCD */ 1072 struct dc_link *link = stream->link; 1073 union down_spread_ctrl old_downspread; 1074 union down_spread_ctrl new_downspread; 1075 1076 if (link->aux_access_disabled) 1077 return; 1078 1079 if (!dm_helpers_dp_read_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL, 1080 &old_downspread.raw, 1081 sizeof(old_downspread))) 1082 return; 1083 1084 new_downspread.raw = old_downspread.raw; 1085 new_downspread.bits.IGNORE_MSA_TIMING_PARAM = 1086 (stream->ignore_msa_timing_param) ? 1 : 0; 1087 1088 if (new_downspread.raw != old_downspread.raw) 1089 dm_helpers_dp_write_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL, 1090 &new_downspread.raw, 1091 sizeof(new_downspread)); 1092 } 1093 1094 bool dm_helpers_dp_handle_test_pattern_request( 1095 struct dc_context *ctx, 1096 const struct dc_link *link, 1097 union link_test_pattern dpcd_test_pattern, 1098 union test_misc dpcd_test_params) 1099 { 1100 enum dp_test_pattern test_pattern; 1101 enum dp_test_pattern_color_space test_pattern_color_space = 1102 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED; 1103 enum dc_color_depth requestColorDepth = COLOR_DEPTH_UNDEFINED; 1104 enum dc_pixel_encoding requestPixelEncoding = PIXEL_ENCODING_UNDEFINED; 1105 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx; 1106 struct pipe_ctx *pipe_ctx = NULL; 1107 struct amdgpu_dm_connector *aconnector = link->priv; 1108 int i; 1109 1110 for (i = 0; i < MAX_PIPES; i++) { 1111 if (pipes[i].stream == NULL) 1112 continue; 1113 1114 if (pipes[i].stream->link == link && !pipes[i].top_pipe && 1115 !pipes[i].prev_odm_pipe) { 1116 pipe_ctx = &pipes[i]; 1117 break; 1118 } 1119 } 1120 1121 if (pipe_ctx == NULL) 1122 return false; 1123 1124 switch (dpcd_test_pattern.bits.PATTERN) { 1125 case LINK_TEST_PATTERN_COLOR_RAMP: 1126 test_pattern = DP_TEST_PATTERN_COLOR_RAMP; 1127 break; 1128 case LINK_TEST_PATTERN_VERTICAL_BARS: 1129 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS; 1130 break; /* black and white */ 1131 case LINK_TEST_PATTERN_COLOR_SQUARES: 1132 test_pattern = (dpcd_test_params.bits.DYN_RANGE == 1133 TEST_DYN_RANGE_VESA ? 1134 DP_TEST_PATTERN_COLOR_SQUARES : 1135 DP_TEST_PATTERN_COLOR_SQUARES_CEA); 1136 break; 1137 default: 1138 test_pattern = DP_TEST_PATTERN_VIDEO_MODE; 1139 break; 1140 } 1141 1142 if (dpcd_test_params.bits.CLR_FORMAT == 0) 1143 test_pattern_color_space = DP_TEST_PATTERN_COLOR_SPACE_RGB; 1144 else 1145 test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ? 1146 DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 : 1147 DP_TEST_PATTERN_COLOR_SPACE_YCBCR601; 1148 1149 switch (dpcd_test_params.bits.BPC) { 1150 case 0: // 6 bits 1151 requestColorDepth = COLOR_DEPTH_666; 1152 break; 1153 case 1: // 8 bits 1154 requestColorDepth = COLOR_DEPTH_888; 1155 break; 1156 case 2: // 10 bits 1157 requestColorDepth = COLOR_DEPTH_101010; 1158 break; 1159 case 3: // 12 bits 1160 requestColorDepth = COLOR_DEPTH_121212; 1161 break; 1162 default: 1163 break; 1164 } 1165 1166 switch (dpcd_test_params.bits.CLR_FORMAT) { 1167 case 0: 1168 requestPixelEncoding = PIXEL_ENCODING_RGB; 1169 break; 1170 case 1: 1171 requestPixelEncoding = PIXEL_ENCODING_YCBCR422; 1172 break; 1173 case 2: 1174 requestPixelEncoding = PIXEL_ENCODING_YCBCR444; 1175 break; 1176 default: 1177 requestPixelEncoding = PIXEL_ENCODING_RGB; 1178 break; 1179 } 1180 1181 if ((requestColorDepth != COLOR_DEPTH_UNDEFINED 1182 && pipe_ctx->stream->timing.display_color_depth != requestColorDepth) 1183 || (requestPixelEncoding != PIXEL_ENCODING_UNDEFINED 1184 && pipe_ctx->stream->timing.pixel_encoding != requestPixelEncoding)) { 1185 DC_LOG_DEBUG("%s: original bpc %d pix encoding %d, changing to %d %d\n", 1186 __func__, 1187 pipe_ctx->stream->timing.display_color_depth, 1188 pipe_ctx->stream->timing.pixel_encoding, 1189 requestColorDepth, 1190 requestPixelEncoding); 1191 pipe_ctx->stream->timing.display_color_depth = requestColorDepth; 1192 pipe_ctx->stream->timing.pixel_encoding = requestPixelEncoding; 1193 1194 dc_link_update_dsc_config(pipe_ctx); 1195 1196 aconnector->timing_changed = true; 1197 /* store current timing */ 1198 if (aconnector->timing_requested) 1199 *aconnector->timing_requested = pipe_ctx->stream->timing; 1200 else 1201 DC_LOG_ERROR("%s: timing storage failed\n", __func__); 1202 1203 } 1204 1205 dc_link_dp_set_test_pattern( 1206 (struct dc_link *) link, 1207 test_pattern, 1208 test_pattern_color_space, 1209 NULL, 1210 NULL, 1211 0); 1212 1213 return false; 1214 } 1215 1216 void dm_set_phyd32clk(struct dc_context *ctx, int freq_khz) 1217 { 1218 // TODO 1219 } 1220 1221 void dm_helpers_enable_periodic_detection(struct dc_context *ctx, bool enable) 1222 { 1223 /* TODO: add periodic detection implementation */ 1224 } 1225 1226 void dm_helpers_dp_mst_update_branch_bandwidth( 1227 struct dc_context *ctx, 1228 struct dc_link *link) 1229 { 1230 // TODO 1231 } 1232 1233 static bool dm_is_freesync_pcon_whitelist(const uint32_t branch_dev_id) 1234 { 1235 bool ret_val = false; 1236 1237 switch (branch_dev_id) { 1238 case DP_BRANCH_DEVICE_ID_0060AD: 1239 case DP_BRANCH_DEVICE_ID_00E04C: 1240 case DP_BRANCH_DEVICE_ID_90CC24: 1241 ret_val = true; 1242 break; 1243 default: 1244 break; 1245 } 1246 1247 return ret_val; 1248 } 1249 1250 enum adaptive_sync_type dm_get_adaptive_sync_support_type(struct dc_link *link) 1251 { 1252 struct dpcd_caps *dpcd_caps = &link->dpcd_caps; 1253 enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE; 1254 1255 switch (dpcd_caps->dongle_type) { 1256 case DISPLAY_DONGLE_DP_HDMI_CONVERTER: 1257 if (dpcd_caps->adaptive_sync_caps.dp_adap_sync_caps.bits.ADAPTIVE_SYNC_SDP_SUPPORT == true && 1258 dpcd_caps->allow_invalid_MSA_timing_param == true && 1259 dm_is_freesync_pcon_whitelist(dpcd_caps->branch_dev_id)) 1260 as_type = FREESYNC_TYPE_PCON_IN_WHITELIST; 1261 break; 1262 default: 1263 break; 1264 } 1265 1266 return as_type; 1267 } 1268